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XMC™ Forum Discussions

Not applicable
Hi,

As far as I understand, when going to deep sleep mode the DCO1(96MHz oscillator) is disabled and then MCLK/PCLK is running from the standby clock (32kHz oscillator DCO2).
When the device wakes up from the deep sleep (e.g. via SysTick interrupt) I see that the MCLK/PCLK is switched back automatically to DCO1.

Is there an option to configure the device in such a way that after wake-up form deep sleep it:
- keeps DCO1(96MHz) off
AND
- runs from the standby clock (32kHz DCO2)?

Thanks.
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10 Replies
User12775
Level 5
Level 5
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As illustrated by the reference manual, it is possible.
2776.attach
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Not applicable
Hi,

Thanks for the feedback.
I know the diagram and it is clear there is a path to feed the DCO2 clock to MCLK/PCLK (as it actually happens during deep sleep mode according to the Reference Manual).
What I did not manage to clarify is the register or register set that have to be modified to:
Set DCO2 as source clock for the MCLK/PCLK domain during normal operation
Is that even possible?
As far as I understand from section 14.5.2 Clock System and Control (attached below), seems like it is not, but that is actually what I would like to clarify in this thread...

By normal operation in the text above I mean:
Setting DCO2 as source for MCLK/PCLK without the need of generating any of the oscillator failure events:

  • 14.5.2.2 Loss of DCO1 Clock Detection and Recovery
  • 14.5.2.5 Loss of external OSC_HP Clock Detection and Recovery
  • etc...


Thanks in advance for your support.

14.5.2 Clock System and Control
Figure 14-4 shows the block diagram of the clock system in XMC1400. It consists of two
on-chip oscillators (DCO1 1) with synchronisation unit and DCO2), 2 oscillators pad
(OSC_HP and OSC_LP to drive external clock), a doubler and a clock control unit
(CCU). DCO1 has a clock output (dco1_clk), running at 48MHz. DCO2 is used to
generate the standby clock running at 32kHz.
The main clock, MCLK, and fast peripherial clock, PCLK, are generated from DCLK
(output of the doubler clock). Input to DCLK can be selected using bit
CLKCR1.DCLKSEL to be either from the DCO1 clock source or the external clock
source via the OSC_HP oscillator.
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Not applicable
Hi,

Could you please help me pointing out e.g.: the register or set of registers to:
Set DCO2 as clock source for MCLK/PCLK
Is that even possible under normal operation (without generating a loss clock situation)?

Thanks!
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User12775
Level 5
Level 5
First like received
I just get the conclusion from the user manual. I have not done the register setting in my application. Maybe you need to dig the user manual for the detail.
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Not applicable
Hi,

I already check all clock related sections of the reference manual without success.
My conclusion is that setting DCO2 as clock source for MCLK/PCLK under normal operation is simply not possible, but would like to have a confirmation e.g.: from an Infineon employee to stop digging and investing time in this topic.

BR.
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jferreira
Employee
Employee
First like received 750 replies posted 500 replies posted
Hi,

It is not possible to use DCO2 as clock source for MCLK/PCLK in normal mode.
What about if you ramp down DCO1 before entering deep sleep mode?

Regards,
Jesus
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Not applicable
Hi Jesus,

Thanks for your answer.

Ramping down DCO1 is our current approach, but the following topic is open:
Which is the maximum MCLK/PCLK frequency allowed before going to deep sleep mode?
I started a new thread for it few days ago:
https://www.infineonforums.com/threads/5304-XMC1400-Maximum-MCLK-PCLK-frequency-before-going-to-deep...
Could you please help us to clarify it?

BR.
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jferreira
Employee
Employee
First like received 750 replies posted 500 replies posted
Hi,

The maximum recommended is 4 times the frequency of DCO2 to prevent a sudden load change that could cause a brownout reset when entering sleep or deep sleep mode.
Actually I would go down to 32KHz.

Regards,
Jesus
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Not applicable
Hi Jesus,

According to:
Table 14-4 PCLK and MCLK frequency range
The frequency range for MCLK when using DCO1 as clock source is: 188kHz - 48MHz

So, even when using the maximum values for IDIV and FDIV, the minimum operating frequency of MCLK (with DCO1) is ~188kHz which is out of the range recommended in the previous reply:
The maximum recommended is 4 times the frequency of DCO2 to prevent a sudden load change that could cause a brownout reset when entering sleep or deep sleep mode.


Perhaps I am missing something here, or miscalculating the frequency range for MCLK when using DCO1 as clock source, but I would find very restrictive if DCO1 cannot be used as as clock source for MCLK when going to sleep/deep-sleep mode.

Could you please help me to clarify the following topics:

  • Is there a risk of producing brownout resets when entering sleep or deep-sleep mode with MCLK=~188kHz?
  • Does it mean that using DCO1 as clock source for MCLK IS NOT compatible with sleep/deep-sleep mode?


Thank you and BR
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Not applicable
Hi Jesus,

According to:
2795.attach
The minimum possible frequency for MCLK when using DCO1 oscillator as clock source is 188KHz, which is out of the range given in your previous reply.

The maximum recommended is 4 times the frequency of DCO2 to prevent a sudden load change that could cause a brownout reset when entering sleep or deep sleep mode


Could you please help us to clarify the following topics?

  • Is there a risk to generate a sudden load change that could cause a brownout reset when going to sleep/deep-sleep with MCLK=188KHz?
  • Does it mean that usage of DCO1 as clock source for MCLK IS NOT compatible with sleep/deep-sleep mode?


Thank you and BR.
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