Hi,
i have some questions related to the ADC of the XMC1302.
1. What is the real difference between the Compatible and the Accelerated Timing Mode? What are the advantages and disadvantages?
2. I know, that in Compatible Timing Mode, the sample time is defined by STCS in Registers GxICLASS or GLOBICLASS (SST has to be 0).
And in Acclerated Timing Mode, the sample time is defined by SST in SHS_TIMCFG.
In Compatible Timing mode, I am able to configure different sample times for different groups (e.g. high-impedance or low-impedance signals).
Can I do this also with the Accelerated Timing Mode?
3. I don't know how to correctly select the Compatible or the Accelerated Timing Mode. For example, if I want to configure the ADC in the compatible Timing mode, is it enough to set SST = 0 and STCS != 0 ???
Or do I have to clear the AT-Bit in Register SHS0_TIMCFG, too??
I don't know exactly what the description of this Bit means.
0 : Compatible Timing: Result available after Standard conversion time
1 : Accelerated Timing: Result available as soon as converted.
4. In Accelerated Timing Mode the Conversion Timing is calculated as follow:
tcn = SST * tADC + 4 * tSH + (N+8) * tSH + 5 * tADC
In Compatible Timing Mode, the Conversion Timing is calculated as follow:
tcn = (2 + STC + N + PC) * tADCI + 2 * tADC
Why is the converter clocked by tSH in the Accelerated Timing mode ((N+8) * tSH) and by tADCI ((...+ N + ...) * tADCI) in the Compatible Timing mode?
I would like to have the sample-time flexibility of the Compatible Timing Mode. But I read, that DIVA must be 3 or greater not to lose accuracy, resulting in fADCI = 32MHz / (3+1) = 8 MHz. So the whole Conversion Timing takes a lot longer than in Accelerated Timing Mode :).
Thx
