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User18316
Level 1
Level 1
Hello,
I am fairly new to the XMC world.

Has anyone an working SPI example for the XMC 4700 that only uses XMC libs? (No Dave apps allowed in my project)

I tried to use the provided XMC 4500 SPI example from the XMC libs.
I changed the ports to my needs, hocked it up to my oscilloscope and i get absolute no signals, not even a clock signal.


Thanks a lot for your support,
Stefan
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7 Replies
User6412
Level 4
Level 4
See my simple example of SPI initialization. Call spi_init() function for initialization.
Read data from USIC1_CH0->OUTR register. Write data into USIC1_CH0->IN register (see datasheet about USIC SPI FIFO).


/**
* Singleton to Reset the USIC1 Unit
*/
void USIC1_Reset(void) {
static uint16_t USIC1_initialized = 0;
if(USIC1_initialized) return;
// Assert reset
SCU_RESET->PRSET1 |= SCU_RESET_PRSET1_USIC1RS_Msk;
// De-assert reset
SCU_RESET->PRCLR1 |= SCU_RESET_PRCLR1_USIC1RS_Msk;
USIC1_initialized++;
}

/**
* Initialization of SPI-Communication
* Communication Module U1C0.
* Signals:
* SPI_DOUT_CurSen_P P0.4 / U1C0.DX0A
* SPI_DIN_CurSen_P P0.5 / U1C0.DOUT0
* SPI_CS_CurSen_P P0.6 / U1C0.SELO0
* SPI_CLK_CurSen_P P0.11 / U1C0.SCLKOUT
*/
void spi_init() {
USIC1_Reset();
do {
USIC1_CH0->KSCFG = USIC_CH_KSCFG_MODEN_Msk |
// The module is switched on and can operate.
// After writing 1 to MODEN, it is recommended
// to read register KSCFG to avoid pipeline
// effects in the control block before accessing
// other USIC registers.
USIC_CH_KSCFG_BPMODEN_Msk;
// Bit Protection for MODEN
} while(USIC1_CH0->KSCFG == 0); // read register KSCFG
USIC1_CH0->PCR_SSCMode = (1UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos & USIC_CH_PCR_SSCMode_MSLSEN_Msk) |
// The MSLS generation is enabled.
// This is the setting for SSC master mode.
(1UL << USIC_CH_PCR_SSCMode_SELCTR_Pos & USIC_CH_PCR_SSCMode_SELCTR_Msk) |
// This bit selects the operating mode for the SELO[7:0]
// outputs. The direct select mode is enabled.
(1UL << USIC_CH_PCR_SSCMode_SELINV_Pos & USIC_CH_PCR_SSCMode_SELINV_Msk) |
// Select Inversion
// This bit defines if the polarity of the SELO[7:0] outputs in
// relation to the master slave select signal MSLS.
// 0B The SELO outputs have the same polarity as the
// MSLS signal (active high).
// 1B The SELO outputs have the inverted polarity to the
// MSLS signal (active low).
(0UL << USIC_CH_PCR_SSCMode_FEM_Pos & USIC_CH_PCR_SSCMode_FEM_Msk) |
// Frame End Mode
// The MSLS signal is kept active also while no new
// data is available and no other end of frame condition
// is reached. In this case, the software can accept
// delays in delivering the data without automatic
// deactivation of MSLS in multi-word data frames.
(0UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos & USIC_CH_PCR_SSCMode_CTQSEL1_Msk) |
// This bit field defines the input frequency fCTQIN for the
// generation of the slave select delays Tiw and Tnf.
// 00B fCTQIN = fPDIV
// 01B fCTQIN = fPPP
// 10B fCTQIN = fSCLK
// 11B fCTQIN = fMCLK
(1UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos & USIC_CH_PCR_SSCMode_PCTQ1_Msk) |
// Divider Factor PCTQ1 for Tiw and Tnf
// This bit field represents the divider factor PCTQ1
// (range = 0 - 3) for the generation of the inter-word delay
// and the next-frame delay.
// Tiw = Tnf = 1/fCTQIN x (PCTQ1 + 1) x (DCTQ1 + 1)
(0UL << USIC_CH_PCR_SSCMode_DCTQ1_Pos & USIC_CH_PCR_SSCMode_DCTQ1_Msk) |
// Divider Factor DCTQ1 for Tiw and Tnf
// This bit field represents the divider factor DCTQ1
// (range = 0 - 31) for the generation of the inter-word delay
// and the next-frame delay.
// Tiw = Tnf = 1/fCTQIN x (PCTQ1 + 1) x (DCTQ1 + 1)
(9UL << USIC_CH_PCR_SSCMode_SELO_Pos & USIC_CH_PCR_SSCMode_SELO_Msk) |
// Select Output
// This bit field defines the setting of the SELO[7:0] output
// lines.
// 0B The corresponding SELOx line cannot be activated.
// 1B The corresponding SELOx line can be activated
// (according to the mode selected by SELCTR).
(0UL << USIC_CH_PCR_SSCMode_TIWEN_Pos & USIC_CH_PCR_SSCMode_TIWEN_Msk);
// Enable Inter-Word Delay Tiw
// This bit enables/disables the inter-word delay Tiw after the
// transmission of a data word.
// 0B No delay between data words of the same frame.
// 1B The inter-word delay Tiw is enabled and introduced
// between data words of the same frame.

USIC1_CH0->DX0CR = (0UL << USIC_CH_DX0CR_DSEL_Pos & USIC_CH_DX0CR_DSEL_Msk) |
// The data input DX0A is selected.
(1UL << USIC_CH_DX0CR_INSW_Pos & USIC_CH_DX0CR_INSW_Msk) |
// Input Switch
// This bit defines if the data shift unit input is derived
// from the input data path DXn or from the selected
// protocol pre-processors.
// 0B The input of the data shift unit is controlled by the
// protocol pre-processor.
// 1B The input of the data shift unit is connected to
// the selected data input line. This setting is used
// if the signals are directly derived from an input
// pin without treatment by the protocol preprocessor.
(1UL << USIC_CH_DX0CR_DFEN_Pos & USIC_CH_DX0CR_DFEN_Msk) |
// Digital Filter Enable
// This bit enables/disables the digital filter for signal
// DXnS.
// 0B The input signal is not digitally filtered.
// 1B The input signal is digitally filtered.
(1UL << USIC_CH_DX0CR_DSEN_Pos & USIC_CH_DX0CR_DSEN_Msk) |
// Data Synchronization Enable
// This bit selects if the asynchronous input signal or the
// synchronized (and optionally filtered) signal DXnS can
// be used as input for the data shift unit.
// 0B The un-synchronized signal can be taken as
// input for the data shift unit.
// 1B The synchronized signal can be taken as input
// for the data shift unit.
(1UL << USIC_CH_DX0CR_DPOL_Pos & USIC_CH_DX0CR_DPOL_Msk) |
// Data Polarity for DXn
// This bit defines the signal polarity of the input signal.
// 0B The input signal is not inverted.
// 1B The input signal is inverted.
(0UL << USIC_CH_DX0CR_SFSEL_Pos & USIC_CH_DX0CR_SFSEL_Msk) |
// Sampling Frequency Selection
// This bit defines the sampling frequency of the digital
// filter for the synchronized signal DXnS.
// 0B The sampling frequency is fPB.
// 1B The sampling frequency is fFD.
(0UL << USIC_CH_DX0CR_CM_Pos & USIC_CH_DX0CR_CM_Msk);
// Combination Mode
// This bit field selects which edge of the synchronized
// (and optionally filtered) signal DXnS actives the trigger
// output DXnT of the input stage.
// 00B The trigger activation is disabled.
// 01B A rising edge activates DXnT.
// 10B A falling edge activates DXnT.
// 11B Both edges activate DXnT.
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User6412
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USIC1_CH0->FDR = (1015UL << USIC_CH_FDR_STEP_Pos & USIC_CH_FDR_STEP_Msk) |
// 16 MHz.
// In normal divider mode STEP contains the reload
// value for RESULT after RESULT has reached 3FFH.
// In fractional divider mode STEP defines the value
// added to RESULT with each input clock cycle.
(1UL << USIC_CH_FDR_DM_Pos & USIC_CH_FDR_DM_Msk);
// Divider Mode
// This bit fields defines the functionality of the
// fractional divider block.
// 00B The divider is switched off, fFD = 0.
// 01B Normal divider mode selected.
// 10B Fractional divider mode selected.
// 11B The divider is switched off, fFD = 0.
USIC1_CH0->BRG = (0UL << USIC_CH_BRG_CLKSEL_Pos & USIC_CH_BRG_CLKSEL_Msk) |
// Clock Selection
// This bit field defines the input frequency fPIN
// 00B The fractional divider frequency fFD is selected.
// 01B Reserved, no action
// 10B The trigger signal DX1T defines fPIN. Signal
// MCLK toggles with fPIN.
// 11B Signal MCLK corresponds to the DX1S signal
// and the frequency fPIN is derived from the rising
// edges of DX1S.
(0UL << USIC_CH_BRG_PPPEN_Pos & USIC_CH_BRG_PPPEN_Msk) |
// Enable 2:1 Divider for fPPP
// This bit defines the input frequency fPPP.
// 0B The 2:1 divider for fPPP is disabled.
// fPPP = fPIN
// 1B The 2:1 divider for fPPP is enabled.
// fPPP = fMCLK = fPIN / 2.
(0UL << USIC_CH_BRG_CTQSEL_Pos & USIC_CH_BRG_CTQSEL_Msk) |
// Input Selection for CTQ
// This bit defines the length of a time quantum for the
// protocol pre-processor.
// 00B fCTQIN = fPDIV
// 01B fCTQIN = fPPP
// 10B fCTQIN = fSCLK
// 11B fCTQIN = fMCLK
(0UL << USIC_CH_BRG_PCTQ_Pos & USIC_CH_BRG_PCTQ_Msk) |
// Pre-Divider for Time Quanta Counter
// This bit field defines length of a time quantum tq for
// the time quanta counter in the protocol pre-processor.
// tQ = (PCTQ + 1) / fCTQIN
(0UL << USIC_CH_BRG_DCTQ_Pos & USIC_CH_BRG_DCTQ_Msk) |
// Denominator for Time Quanta Counter
// This bit field defines the number of time quanta tq
// taken into account by the time quanta counter in the
// protocol pre-processor.
(3UL << USIC_CH_BRG_PDIV_Pos & USIC_CH_BRG_PDIV_Msk) |
// Divider Mode: Divider Factor to Generate fPDIV
// This bit field defines the ratio between the input
// frequency fPPP and the divider frequency fPDIV.
// 16MHz / 4 = 4MHz
(0UL << USIC_CH_BRG_SCLKOSEL_Pos & USIC_CH_BRG_SCLKOSEL_Msk) |
// Shift Clock Output Select
// This bit field selects the input source for the
// SCLKOUT signal.
// 0B SCLK from the baud rate generator is selected
// as the SCLKOUT input source.
// 1B The transmit shift clock from DX1 input stage is
// selected as the SCLKOUT input source.
// Note: The setting SCLKOSEL = 1 is used only when
// complete closed loop delay compensation is
// required for a slave SSC/IIS. The default
// setting of SCLKOSEL = 0 should be always
// used for all other cases.
(2UL << USIC_CH_BRG_SCLKCFG_Pos & USIC_CH_BRG_SCLKCFG_Msk);
// Shift Clock Output Configuration
// This bit field defines the level of the passive phase of
// the SCLKOUT signal and enables/disables a delay of
// half of a SCLK period.
// 00B The passive level is 0 and the delay is disabled.
// 01B The passive level is 1 and the delay is disabled.
// 10B The passive level is 0 and the delay is enabled.
// 11B The passive level is 1 and the delay is enabled.

USIC1_CH0->SCTR = (1UL << USIC_CH_SCTR_SDIR_Pos & USIC_CH_SCTR_SDIR_Msk) |
// Shift Direction
// This bit defines the shift direction of the data words for
// transmission and reception.
// 0B Shift LSB first. The first data bit of a data word
// is located at bit position 0.
// 1B Shift MSB first. The first data bit of a data word
// is located at the bit position given by bit field
// SCTR.WLE.
(0UL << USIC_CH_SCTR_PDL_Pos & USIC_CH_SCTR_PDL_Msk) |
// Passive Data Level
// This bit defines the output level at the shift data output
// signal when no data is available for transmission. The
// PDL level is output with the first relevant transmit shift
// clock edge of a data word.
// 0B The passive data level is 0.
// 1B The passive data level is 1.
(0UL << USIC_CH_SCTR_DOCFG_Pos & USIC_CH_SCTR_DOCFG_Msk) |
// Data Output Configuration
// This bit defines the relation between the internal shift
// data value and the data output signal DOUTx.
// X0B DOUTx = shift data value
// X1B DOUTx = inverted shift data value
(1UL << USIC_CH_SCTR_TRM_Pos & USIC_CH_SCTR_TRM_Msk) |
// Transmission Mode
// This bit field describes how the shift control signal is
// interpreted by the DSU. Data transfers are only
// possible while the shift control signal is active.
// 00B The shift control signal is considered as inactive
// and data frame transfers are not possible.
// 01B The shift control signal is considered active if it
// is at 1-level. This is the setting to be
// programmed to allow data transfers.
// 10B The shift control signal is considered active if it
// is at 0-level. It is recommended to avoid this
// setting and to use the inversion in the DX2
// stage in case of a low-active signal.
// 11B The shift control signal is considered active
// without referring to the actual signal level. Data
// frame transfer is possible after each edge of the
// signal.
(23UL << USIC_CH_SCTR_FLE_Pos & USIC_CH_SCTR_FLE_Msk) |
// Frame Length (17 bit)
// This bit field defines how many bits are transferred
// within a data frame. A data frame can consist of
// several concatenated data words.
// If TCSR.FLEMD = 1, the value can be updated
// automatically by the data handler.
(7UL << USIC_CH_SCTR_WLE_Pos & USIC_CH_SCTR_WLE_Msk);
// Word Length
// This bit field defines the data word length (amount of
// bits that are transferred in each data word) for
// reception and transmission. The data word is always
// right-aligned in the data buffer at the bit positions
// [WLE down to 0].
// If TCSR.WLEMD = 1, the value can be updated
// automatically by the data handler.
// 0H The data word contains 1 data bit located at bit
// position 0.
// 1H The data word contains 2 data bits located at bit
// positions [1:0].
// ...
// EH The data word contains 15 data bits located at
// bit positions [14:0].
// FH The data word contains 16 data bits located at
// bit positions [15:0].
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User6412
Level 4
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USIC1_CH0->TCSR = (1UL << USIC_CH_TCSR_TDSSM_Pos & USIC_CH_TCSR_TDSSM_Msk) |
// TBUF Data Single Shot Mode
// This bit defines if the data word TBUF data is
// considered as permanently valid or if the data should
// only be transferred once.
// 0B The data word in TBUF is not considered as
// invalid after it has been loaded into the transmit
// shift register. The loading of the TBUF data into
// the shift register does not clear TDV.
// 1B The data word in TBUF is considered as invalid
// after it has been loaded into the shift register. In
// ASC and IIC mode, TDV is cleared with the TBI
// event, whereas in SSC and IIS mode, it is
// cleared with the RSI event.
// TDSSM = 1 has to be programmed if an
// optional data buffer is used.
(1UL << USIC_CH_TCSR_SELMD_Pos & USIC_CH_TCSR_SELMD_Msk) |
// The automatic update of PCR.CTR[23:16] is
// enabled.
(1UL << USIC_CH_TCSR_TDEN_Pos & USIC_CH_TCSR_TDEN_Msk);
// TBUF Data Enable
// This bit field controls the gating of the transmission
// start of the data word in the transmit buffer TBUF.
// 00B A transmission start of the data word in TBUF is
// disabled. If a transmission is started, the
// passive data level is sent out.
// 01B A transmission of the data word in TBUF can be
// started if TDV = 1.
// 10B A transmission of the data word in TBUF can be
// started if TDV = 1 while DX2S = 0.
// 11B A transmission of the data word in TBUF can be
// started if TDV = 1 while DX2S = 1.

/**
* FIFO Configuration (USIC1_CH0)
* (Note: see also the USIC1_CH1 FIFO)
*/

USIC1_CH0->TBCTR = (0UL << USIC_CH_TBCTR_DPTR_Pos & USIC_CH_TBCTR_DPTR_Msk) |
// Data Pointer
// This bit field defines the start value for the transmit
// buffer pointers when assigning the FIFO entries to
// the transmit FIFO buffer. A read always delivers 0.
// When writing DPTR while SIZE = 0, both transmitter
// pointers TDIPTR and RTDOPTR in register
// TRBPTR are updated with the written value and the
// buffer is considered as empty. A write access to
// DPTR while SIZE > 0 is ignored and does not modify
// the pointers.
(4UL << USIC_CH_TBCTR_SIZE_Pos & USIC_CH_TBCTR_SIZE_Msk);
// Buffer Size
// This bit field defines the number of FIFO entries
// assigned to the transmit FIFO buffer.
// 000B The FIFO mechanism is disabled. The buffer
// does not accept any request for data.
// 001B The FIFO buffer contains 2 entries.
// 010B The FIFO buffer contains 4 entries.
// 011B The FIFO buffer contains 8 entries.
// 100B The FIFO buffer contains 16 entries.
// 101B The FIFO buffer contains 32 entries.
// 110B The FIFO buffer contains 64 entries.
// 111B Reserved

USIC1_CH0->RBCTR = (16UL << USIC_CH_RBCTR_DPTR_Pos & USIC_CH_RBCTR_DPTR_Msk) |
// Data Pointer
// This bit field defines the start value for the receive
// buffer pointers when assigning the FIFO entries to
// the receive FIFO buffer. A read always delivers 0.
// When writing DPTR while SIZE = 0, both receiver
// pointers RDIPTR and RDOPTR in register TRBPTR
// are updated with the written value and the buffer is
// considered as empty. A write access to DPTR while
// SIZE > 0 is ignored and does not modify the
// pointers.
(4UL << USIC_CH_RBCTR_SIZE_Pos & USIC_CH_RBCTR_SIZE_Msk);
// Buffer Size
// This bit field defines the number of FIFO entries
// assigned to the receive FIFO buffer.
// 000B The FIFO mechanism is disabled. The buffer
// does not accept any request for data.
// 001B The FIFO buffer contains 2 entries.
// 010B The FIFO buffer contains 4 entries.
// 011B The FIFO buffer contains 8 entries.
// 100B The FIFO buffer contains 16 entries.
// 101B The FIFO buffer contains 32 entries.
// 110B The FIFO buffer contains 64 entries.
// 111B Reserved

USIC1_CH0->CCR = (1UL << USIC_CH_CCR_MODE_Pos & USIC_CH_CCR_MODE_Msk);
// 1H The SSC (SPI) protocol is selected.

// SPI_DIN_CurSen_P P0.5 / U1C0.DOUT0 ALT2
WR_REG(PORT0->IOCR4, PORT0_IOCR4_PC5_Msk, PORT0_IOCR4_PC5_Pos, 0b10010);
// SPI_CS_CurSen_P P0.6 / U1C0.SELO0 ALT2
WR_REG(PORT0->IOCR4, PORT0_IOCR4_PC6_Msk, PORT0_IOCR4_PC6_Pos, 0b10010);
// SPI_CLK_CurSen_P P0.11 / U1C0.SCLKOUT ALT2
WR_REG(PORT0->IOCR8, PORT0_IOCR8_PC11_Msk, PORT0_IOCR8_PC11_Pos, 0b10010);
}
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User16529
Level 4
Level 4
First solution authored
Check the xmc4800 automation board start example. You can find it at the infineon web site

https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc48_aut_base_v2/

in the section tools & software download the first zip
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User18316
Level 1
Level 1
Thanks for your reply but the 4800 example was build with Dave apps.
I am not alowed to use Dave apps.
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User16529
Level 4
Level 4
First solution authored
the apps are only for the ethercat part. SPI is implemented with libraries. I'm exploiting this example to implement SPI without dave apps
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User18316
Level 1
Level 1
Janet wrote:
the apps are only for the ethercat part. SPI is implemented with libraries. I'm exploiting this example to implement SPI without dave apps


Thanks, I found it. 🙂
I will give it a try later the evening!
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