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User11185
Level 1
Level 1
I would like to sample an analog signal connected at channel CH1-G0 at 25Khz (sample time 40 usec). To reduce to CPU load, my intention is store the conversion result in the FIFO buffer with 6 concatenated result registers (ResReg5 to ResReg0) and having an interrupt every 6 conversions. In the interrupt function the 6 result values are read and elaborated. To reduce the CPU load I don’t want to have an interrupt for each sample (40usec) but once every 6 sample (240usec).
At the moment I have an implementation in which the conversion of Ch1- G0 is executed every 40 usec using the “Scan Request Source” triggered by the CCU4 timer.
I’m using the FIFO buffer programming the result register in the following way :
CH1-> ResReg5 -INPUT STAGE – FEN= 0 -Result event interrupt = 0
ResReg4 -INTERMEDIATE STAGE – FEN=1 - Result event interrupt = 0
ResReg3 -INTERMEDIATE STAGE – FEN=1 - Result event interrupt = 0
ResReg2 -INTERMEDIATE STAGE – FEN=1 - Result event interrupt = 0
ResReg1 -INTERMEDIATE STAGE – FEN=1 - Result event interrupt = 0
ResReg0 -OUTPUT STAGE – FEN=1 – Result event interrupt = 1

Unfortunately I always have an interrupt for each conversion in other word an interrupt every 40 usec!!
Is it possible in same way achieve the condition descripted above?
Many thanks 🙂
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7 Replies
Not applicable
Why not using DMA in Multi-Blocktransfer-Mode using the adc_conv_complt_event as a trigger for the DMA?

ADC_Result - > DMA -> Dst_buffer[6]


For more information check AP32290
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Travis
Employee
Employee
First like received
Hi Enzo,

Attached is an VADC example using FIFO method. However this is base on DAVE3.
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User11185
Level 1
Level 1
SMeinzer wrote:
Why not using DMA in Multi-Blocktransfer-Mode using the adc_conv_complt_event as a trigger for the DMA?

ADC_Result - > DMA -> Dst_buffer[6]


For more information check AP32290


Hello SMeinzer!!

at the moment I'm using the XMC4500 because I have an evaluation board only for it (Hexagon board) but the intention for the final board is to use the cheaper XMC 1400 and , as far as I know , it hasn't a DMA channel.
Sorry if I have not tell all these information from the beginning , and in ani case thank you for your help!! 🙂

Enzo
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User11185
Level 1
Level 1
Travis wrote:
Hi Enzo,

Attached is an VADC example using FIFO method. However this is base on DAVE3.


Hello Travis,

I have checked the example but he is different from my intention that are the following:
sample an analog signal at 25kHz (sample time 40 usec). The conversion results should be buffered in automatic (I mean no SW interrupt) in the FIFO buffer and I would have a SW interrupt every 6 sample results , that means when the conversion result is written in the last result register of the FIFO (OUTPUT STAGE, interrupt routine every 40usec x 6 = 240 usec). Is this possible using an XMC 1400 (no DMA channel) ?
I have seen the possibility to store the conversion results in the FIFO buffer. I did some trials with an evaluation kit connecting the analogic signal to the CH1G0. Then I have done an implementation in which the conversion of the CH1G0 is executed every 40 usec using the “Scan Request Source” triggered by the CCU4 timer. The conversion results are stored in the FIFO buffer :
ResReg5 INPUT STAGE Result Event Interrupt = 0
ResReg4 FEN=1 INTERMEDIATE STAGE Result Event Interrupt = 0
ResReg3 FEN=1 INTERMEDIATE STAGE Result Event Interrupt = 0
ResReg2 FEN=1 INTERMEDIATE STAGE Result Event Interrupt = 0
ResReg1 FEN=1 INTERMEDIATE STAGE Result Event Interrupt = 0
ResReg0 FEN=1 OUTPUT STAGE Result Event Interrupt = 1
Unfortunately I always have an interrupt for each conversion in other word an interrupt every 40 usec!!
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Travis
Employee
Employee
First like received
Hi,

The behavior I got is that, at every trigger it will do 6 conversions which ultimately fills up the FIFO Result registers and cause an interrupt.

1827.attach

From the user manual I found this statement

1826.attach
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Travis
Employee
Employee
First like received
Well it's a disappointment to know that the VADC FIFO is not able to function to your expectation.

From the user manual it states that the interrupt event will be triggered at the output stage, which means the very first converted data that is being pushed to the output stage will trigger an interrupt.
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User11185
Level 1
Level 1
Travis wrote:
Well it's a disappointment to know that the VADC FIFO is not able to function to your expectation.

From the user manual it states that the interrupt event will be triggered at the output stage, which means the very first converted data that is being pushed to the output stage will trigger an interrupt.


Many thanks Travis for your support 🙂
Enzo
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