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kalsi
Employee
Employee
10 questions asked 10 sign-ins 5 questions asked

Hello team,

Hope you are doing well.

When you get a chance would you mind sharing some insight into differences between TCPWM (PSoC 62) vs. CCU 4/8 (XMC 4400)?

Regards,

Randhir

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Aashita_R
Moderator
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50 likes received 100 solutions authored 250 replies posted

Hi @kalsi ,

Here are few brief points that distinguish between TCPWM block in PSoC 62 and CCU4/CCU8 in XMC 4400 - 

TCPWM :

  1. There are eight 32 bit TCPWMs and twenty-four 16 bit TCPWMs in PSoC 62 device.
  2. Each TCPWM block can contain up to 32 counters, where each counter can be 16 or 32 bit wide.
  3. The counter block can function in 6 operational modes namely timers, counters, quadrature decoder, PWM, PWM with dead time insertion, PWM with pseudo noise.
  4. There are complementary outputs for each PWM block.
  5. TCPWM block supports interrupt on terminal count and capture count.
  6. There are 3 dedicated registers for TCPWM, namely compare, counter, period.
  7. TCPWM block provides a dedicated interrupt o/p for each counter.
  8. Each block has 14 trigger input signals coming from different peripherals.
  9. Each counter can generate 3 trigger output events such as overflow, underflow and capture compare.

For more details on TCPWM, please go through the Architecture TRM of PSoC 62.

CCU4/CCU8 :

The points mentioned here mostly pertain to the CCU4 block. However, it can also be traced to the CCU8 block.

  1. Each CCU4 block contain 4 identical 16-bit capture/compare timer slices.
  2. Each of the alternate timer slices can only be concatenated.
  3. Due to slice concatenation, up to 64 bit timing operations are possible giving room for flexible frequency measurement.
  4. There are 1 counter, 1 period and 4 capture registers that can work in parallel associated with each of the CCU4 block .
  5. PWM comes with dithering support which is important in functionalities used with very slow control loops that cannot update the period/compare values in fast manner.
  6. Each timer slice can work independently.
  7. Both period and compare register have an aggregated shadow register which enables the update of the PWM and duty cycle on the fly.
  8. Each block has 4 independent PWM signals and 4 service request lines.

For more details, please refer XMC 4400 reference manual.

Best Regards,

Aashita

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2 Replies
Aashita_R
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 250 replies posted

Hi @kalsi ,

Here are few brief points that distinguish between TCPWM block in PSoC 62 and CCU4/CCU8 in XMC 4400 - 

TCPWM :

  1. There are eight 32 bit TCPWMs and twenty-four 16 bit TCPWMs in PSoC 62 device.
  2. Each TCPWM block can contain up to 32 counters, where each counter can be 16 or 32 bit wide.
  3. The counter block can function in 6 operational modes namely timers, counters, quadrature decoder, PWM, PWM with dead time insertion, PWM with pseudo noise.
  4. There are complementary outputs for each PWM block.
  5. TCPWM block supports interrupt on terminal count and capture count.
  6. There are 3 dedicated registers for TCPWM, namely compare, counter, period.
  7. TCPWM block provides a dedicated interrupt o/p for each counter.
  8. Each block has 14 trigger input signals coming from different peripherals.
  9. Each counter can generate 3 trigger output events such as overflow, underflow and capture compare.

For more details on TCPWM, please go through the Architecture TRM of PSoC 62.

CCU4/CCU8 :

The points mentioned here mostly pertain to the CCU4 block. However, it can also be traced to the CCU8 block.

  1. Each CCU4 block contain 4 identical 16-bit capture/compare timer slices.
  2. Each of the alternate timer slices can only be concatenated.
  3. Due to slice concatenation, up to 64 bit timing operations are possible giving room for flexible frequency measurement.
  4. There are 1 counter, 1 period and 4 capture registers that can work in parallel associated with each of the CCU4 block .
  5. PWM comes with dithering support which is important in functionalities used with very slow control loops that cannot update the period/compare values in fast manner.
  6. Each timer slice can work independently.
  7. Both period and compare register have an aggregated shadow register which enables the update of the PWM and duty cycle on the fly.
  8. Each block has 4 independent PWM signals and 4 service request lines.

For more details, please refer XMC 4400 reference manual.

Best Regards,

Aashita

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kalsi
Employee
Employee
10 questions asked 10 sign-ins 5 questions asked

Thanks Aashita.