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Not applicable
Hi,

in the Reference Manual of the XMC 4400 I found the application which I want to realize with the XMC4400 on Page 22-10 "Digital Peak Current Control".
I tried to initialize the HRPWM HRC0 and CSG0 for this application, but it doesn t work. I did this with C Code following the Initialization sequence printed in the Refernce Manuel for the HRPWM.

Do you have some application projects without Dave apps for my application?

Thanks for any answer.

Best regards,
Benedikt
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1 Solution
Halim
Employee
Employee
First question asked First reply posted First solution authored
Hi Benedikt

Please find the example code on initializing the CSG0 and HRC0 attached below.
You can include this subroutine in your project. No apps are required.

Let me know if there is anything else I can help you. 🙂

Regards
Halim


uint8_t HRPWM_CSG_Init(void)
{
int i,HRReady;

//remove the HRPWM from reset -> SCU
SCU_RESET->PRCLR0 |= 0x00800080;
SCU_CLK->CLKSET |= SCU_CLK_CLKSET_CCUCEN_Msk;
SCU_CLK->CGATCLR0 |= 0x00800080;//HRPWM+CCU8

HRPWM0->HRBSC |= 0x100; //Enable HRPWM bias
HRPWM0->CSGCFG |= 0x03; //Set CSG0 high speed mode


/* CSG 0 settings*/
//Slope Generation
HRPWM0_CSG0->DCI = 0x00000020; //Select CCU80 Slice 0 Status as start control
HRPWM0_CSG0->IES = 0x00000008; //Select falling edge for start control

HRPWM0_CSG0->SC = (3 << HRPWM0_CSG0_SC_PSRM_Pos & HRPWM0_CSG0_SC_PSRM_Msk) | //Clear & start for external start config
(0 << HRPWM0_CSG0_SC_FPD_Pos & HRPWM0_CSG0_SC_FPD_Msk) |
(1 << HRPWM0_CSG0_SC_PSV_Pos & HRPWM0_CSG0_SC_PSV_Msk) | //Step clock prescaler set to 4, step clock = (80MHz/4)/2 = 10Mhz
(1 << HRPWM0_CSG0_SC_SCM_Pos & HRPWM0_CSG0_SC_SCM_Msk) | //Select Decrementing slope generation
(1 << HRPWM0_CSG0_SC_SSRM_Pos & HRPWM0_CSG0_SC_SSRM_Msk) | //Start/restart slope generation
(1 << HRPWM0_CSG0_SC_SWSM_Pos & HRPWM0_CSG0_SC_SWSM_Msk) | //CSG0DSV1 is fed to DAC at initial
(1 << HRPWM0_CSG0_SC_PSE_Pos & HRPWM0_CSG0_SC_PSE_Msk); //Pulse swallow enabled

HRPWM0_CSG0 ->SDSV1 = 150; //0x100;
// Pulse Swallow shadow register
HRPWM0_CSG0 ->SPC = 0; //4LSB

//Shadow transfer
HRPWM0->CSGTRG |= 0x01;

//Setup Blanking.
//Set blanking trigger to CCU80 slice 0 status
//Set blanking mode to:high to low transition
HRPWM0_CSG0->CC = 0x00018002;
HRPWM0_CSG0->BLV = 40; //40*12.5ns = 500nsec blanking time.


//Enabling
HRPWM0->HRBSC |=HRPWM0_HRBSC_HRBE_Msk;

//setting the clock info for the HRCs as 80 MHz
HRPWM0 ->HRCCFG = (0x1 << HRPWM0_HRCCFG_HRCPM_Pos & HRPWM0_HRCCFG_HRCPM_Msk ) |
//HR logic ON
(0x3 << HRPWM0_HRCCFG_CLKC_Pos & HRPWM0_HRCCFG_CLKC_Msk ) |
//80MHz
(0x1 << HRPWM0_HRCCFG_HRC0E_Pos & HRPWM0_HRCCFG_HRC0E_Msk) |
//Enable HRC0 high resolution path
(0x1 << HRPWM0_HRCCFG_HRC2E_Pos & HRPWM0_HRCCFG_HRC2E_Msk) ;
//Enable HRC2 high resolution path

/* HRC0 Settings*/
HRPWM0_HRC0->GC = (0x2 << HRPWM0_HRC0_GC_HRM0_Pos & HRPWM0_HRC0_GC_HRM0_Msk) |
//For source 0, both edges positioning is enabled
(0x1 << HRPWM0_HRC0_GC_STC_Pos & HRPWM0_HRC0_GC_STC_Msk);
//Shadow transfer enable for HRC0CR1 and HRC0CR1 linked with CCU8x


HRPWM0_HRC0->GSEL = (0x2 << HRPWM0_HRC0_GSEL_S0ES_Pos & HRPWM0_HRC0_GSEL_S0ES_Msk ) |
//set is high to low of CCU ST in source 0
(0x1 << HRPWM0_HRC0_GSEL_C0ES_Pos & HRPWM0_HRC0_GSEL_C0ES_Msk );
//clear is low to high of CCU ST in source 0

HRPWM0_HRC0->TSEL = (0x0 << HRPWM0_HRC0_TSEL_TSEL0_Pos & HRPWM0_HRC0_TSEL_TSEL0_Msk);

//Enables the dead time generation
//HRPWM0_HRC0->GC |= 0x00000100;

//sets the duty cycle adjustment of rising
HRPWM0_HRC0->SDCR = 0;
//sets the duty cycle adjustment of falling
HRPWM0_HRC0->SDCF = 0;

//requests the shadow transfer for the compare and dead time values
HRPWM0->HRCSTRG = 0x03;

for(i=0;i<0x1FFF;i++);//wait more than 2 microseconds

HRPWM0->GLBANA |= HRPWM0_GLBANA_GHREN_Msk;

HRPWM0->CSGCLRG |= 0x04;

HRPWM0->CSGSETG |= 0x01; // set DAC run bit

HRPWM0->CSGSETG |= 0x02; // set comparator run bit

//Check if the High resolution is ready
HRReady = (((HRPWM0->HRGHRS)&0xffffffff) >> 0);
if(HRReady == 1)
return 0;
else
return 1;

}

View solution in original post

4 Replies
Halim
Employee
Employee
First question asked First reply posted First solution authored
Hi Benedikt

Please find the example code on initializing the CSG0 and HRC0 attached below.
You can include this subroutine in your project. No apps are required.

Let me know if there is anything else I can help you. 🙂

Regards
Halim


uint8_t HRPWM_CSG_Init(void)
{
int i,HRReady;

//remove the HRPWM from reset -> SCU
SCU_RESET->PRCLR0 |= 0x00800080;
SCU_CLK->CLKSET |= SCU_CLK_CLKSET_CCUCEN_Msk;
SCU_CLK->CGATCLR0 |= 0x00800080;//HRPWM+CCU8

HRPWM0->HRBSC |= 0x100; //Enable HRPWM bias
HRPWM0->CSGCFG |= 0x03; //Set CSG0 high speed mode


/* CSG 0 settings*/
//Slope Generation
HRPWM0_CSG0->DCI = 0x00000020; //Select CCU80 Slice 0 Status as start control
HRPWM0_CSG0->IES = 0x00000008; //Select falling edge for start control

HRPWM0_CSG0->SC = (3 << HRPWM0_CSG0_SC_PSRM_Pos & HRPWM0_CSG0_SC_PSRM_Msk) | //Clear & start for external start config
(0 << HRPWM0_CSG0_SC_FPD_Pos & HRPWM0_CSG0_SC_FPD_Msk) |
(1 << HRPWM0_CSG0_SC_PSV_Pos & HRPWM0_CSG0_SC_PSV_Msk) | //Step clock prescaler set to 4, step clock = (80MHz/4)/2 = 10Mhz
(1 << HRPWM0_CSG0_SC_SCM_Pos & HRPWM0_CSG0_SC_SCM_Msk) | //Select Decrementing slope generation
(1 << HRPWM0_CSG0_SC_SSRM_Pos & HRPWM0_CSG0_SC_SSRM_Msk) | //Start/restart slope generation
(1 << HRPWM0_CSG0_SC_SWSM_Pos & HRPWM0_CSG0_SC_SWSM_Msk) | //CSG0DSV1 is fed to DAC at initial
(1 << HRPWM0_CSG0_SC_PSE_Pos & HRPWM0_CSG0_SC_PSE_Msk); //Pulse swallow enabled

HRPWM0_CSG0 ->SDSV1 = 150; //0x100;
// Pulse Swallow shadow register
HRPWM0_CSG0 ->SPC = 0; //4LSB

//Shadow transfer
HRPWM0->CSGTRG |= 0x01;

//Setup Blanking.
//Set blanking trigger to CCU80 slice 0 status
//Set blanking mode to:high to low transition
HRPWM0_CSG0->CC = 0x00018002;
HRPWM0_CSG0->BLV = 40; //40*12.5ns = 500nsec blanking time.


//Enabling
HRPWM0->HRBSC |=HRPWM0_HRBSC_HRBE_Msk;

//setting the clock info for the HRCs as 80 MHz
HRPWM0 ->HRCCFG = (0x1 << HRPWM0_HRCCFG_HRCPM_Pos & HRPWM0_HRCCFG_HRCPM_Msk ) |
//HR logic ON
(0x3 << HRPWM0_HRCCFG_CLKC_Pos & HRPWM0_HRCCFG_CLKC_Msk ) |
//80MHz
(0x1 << HRPWM0_HRCCFG_HRC0E_Pos & HRPWM0_HRCCFG_HRC0E_Msk) |
//Enable HRC0 high resolution path
(0x1 << HRPWM0_HRCCFG_HRC2E_Pos & HRPWM0_HRCCFG_HRC2E_Msk) ;
//Enable HRC2 high resolution path

/* HRC0 Settings*/
HRPWM0_HRC0->GC = (0x2 << HRPWM0_HRC0_GC_HRM0_Pos & HRPWM0_HRC0_GC_HRM0_Msk) |
//For source 0, both edges positioning is enabled
(0x1 << HRPWM0_HRC0_GC_STC_Pos & HRPWM0_HRC0_GC_STC_Msk);
//Shadow transfer enable for HRC0CR1 and HRC0CR1 linked with CCU8x


HRPWM0_HRC0->GSEL = (0x2 << HRPWM0_HRC0_GSEL_S0ES_Pos & HRPWM0_HRC0_GSEL_S0ES_Msk ) |
//set is high to low of CCU ST in source 0
(0x1 << HRPWM0_HRC0_GSEL_C0ES_Pos & HRPWM0_HRC0_GSEL_C0ES_Msk );
//clear is low to high of CCU ST in source 0

HRPWM0_HRC0->TSEL = (0x0 << HRPWM0_HRC0_TSEL_TSEL0_Pos & HRPWM0_HRC0_TSEL_TSEL0_Msk);

//Enables the dead time generation
//HRPWM0_HRC0->GC |= 0x00000100;

//sets the duty cycle adjustment of rising
HRPWM0_HRC0->SDCR = 0;
//sets the duty cycle adjustment of falling
HRPWM0_HRC0->SDCF = 0;

//requests the shadow transfer for the compare and dead time values
HRPWM0->HRCSTRG = 0x03;

for(i=0;i<0x1FFF;i++);//wait more than 2 microseconds

HRPWM0->GLBANA |= HRPWM0_GLBANA_GHREN_Msk;

HRPWM0->CSGCLRG |= 0x04;

HRPWM0->CSGSETG |= 0x01; // set DAC run bit

HRPWM0->CSGSETG |= 0x02; // set comparator run bit

//Check if the High resolution is ready
HRReady = (((HRPWM0->HRGHRS)&0xffffffff) >> 0);
if(HRReady == 1)
return 0;
else
return 1;

}
Farzad
Level 1
Level 1
First reply posted First like given Welcome!

Thank you. That helped me a lot.

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Not applicable
Thanks for you code!
I already set up the HRPWM without your code, but your code gave me some helpful comments.
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User21480
Level 1
Level 1
First reply posted First question asked
hii Benedikt

please share your template code am also working on HRPWM for 3kw DCDC for generating complimentry PWMs
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