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louishoppe
Employee
Employee
5 sign-ins First question asked First reply posted

Hello,
im writing a program for XMC 1300 in DAVE which includes SPI and EEPROM. 
My program breaks into hard fault handler when enabling an Timer Interrupt so i want to know why.
Can someone please give me a step by step tutorial how to get the reason for this?
I know that i should take a look at the CFSR Register, but i don't know how.

Thank you in Advance,

Louis

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Pradeep_PN
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 100 solutions authored

Hi @louishoppe ,

XMC 1300 has Arm cortex m0 which doesn't have CFSR(Configurable fault status register) or HFSR(Hard fault status register) registers.

So it is not possible to debug the hard fault on Arm cortex m0 using the mentioned registers.

As you have mentioned your program breaks into hard fault handler when enabling the timer interrupt.

So please follow below steps.

1)We suggest you start debugging and put a break point at the start of  enabling timer interrupt function .

2)Then run your program until you hit the break point.

3)Then step into until you reach the line that is causing the hard fault.

4)You can confirm it by observing the IPSR register (Where a value of 0x3 indicates a hard fault)

Below guide gives you the potential causes of the hard fault in the Fault Handling section.

Link : https://developer.arm.com/documentation/dui0497/a/the-cortex-m0-processor/fault-handling?lang=en

Please refer to the below thread which may help you.

Link : https://community.infineon.com/t5/PSoC-4/Is-ther-HFSR-Hard-fault-status-register-in-cortex-M0/td-p/3...

Hope this helps and let me know if you have nay further queries.

Best Regards
Pradeep

 

 

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Pradeep_PN
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 100 solutions authored

Hi @louishoppe ,

XMC 1300 has Arm cortex m0 which doesn't have CFSR(Configurable fault status register) or HFSR(Hard fault status register) registers.

So it is not possible to debug the hard fault on Arm cortex m0 using the mentioned registers.

As you have mentioned your program breaks into hard fault handler when enabling the timer interrupt.

So please follow below steps.

1)We suggest you start debugging and put a break point at the start of  enabling timer interrupt function .

2)Then run your program until you hit the break point.

3)Then step into until you reach the line that is causing the hard fault.

4)You can confirm it by observing the IPSR register (Where a value of 0x3 indicates a hard fault)

Below guide gives you the potential causes of the hard fault in the Fault Handling section.

Link : https://developer.arm.com/documentation/dui0497/a/the-cortex-m0-processor/fault-handling?lang=en

Please refer to the below thread which may help you.

Link : https://community.infineon.com/t5/PSoC-4/Is-ther-HFSR-Hard-fault-status-register-in-cortex-M0/td-p/3...

Hope this helps and let me know if you have nay further queries.

Best Regards
Pradeep

 

 

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louishoppe
Employee
Employee
5 sign-ins First question asked First reply posted

Thank you for your answer. I Guess that's why i couldn't find anything about it for XMC 1300. Good to know.
I already worked my way through the Code with breakpoints and it always crashed while waiting for an Interrupt Event of an Systimer.  When deleting some (random) lines of Code it worked fine. Turns out it got into Stack Overflow because it couldn't catch up with all the periodic Interrupts i have for ADC, LCD Display, Peripherals etc..  Increasing the stack_size in the linker_script.ld to 2048 solved the Issue.

Anyways, thank you for your help.

Greetings, Louis

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