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I have a function, that contains a small section of code, that should not be interrupted. I wrap that section, in the usual __disable_irq() before, and __enable_irq() after.

As it happens, I need to call this function from various places, some of which, are within an ISR.

In some official docs, I've read that an EXC_RETURN value loaded into PC, at the end of an ISR, is what marks the end of the ISR, and allows the CPU to take another interrupt, if one is pending.

But in other official docs, I've read that the __enable_irq(), allows all interrupts to be taken.

Which is correct ?

I'm concerned that the __enable_irq(), within my function, when called from an ISR, would allow another interrupt to be taken, before my ISR finishes executing.

Best regards,

2 Replies
Level 1
Level 1
I believe you're correct that calling __enable_irq() inside your function (inside an ISR) will prematurely re-enable interrupts.

I'm new to XMC chips but I can speak to how it's done in other processors. I'd bet the XMC system is similar.

In AVR, for instance, there is a single bit in the SREG register than controls whether or not interrupts are currently enabled. So, for critical sections, you store the SREG into some temporary, then disable interrupts. At the end of the critical section, you restore the SREG from the temporary. If interrupts were on before, they turn back on. If they were off, nothing happens.

Alternatively, you could make two versions of your function. One that does disable interrupts and one that does not just for use in ISRs.
Level 5
Level 5
First solution authored First like received
__enable_irq() and __disable_irq() switch on and off a general Interrupt Mask bit in the cortex arm core.
The relationship between this mask bit and individual interrupt enable bit is AND.

If you call __enable_irq() in your ISR and at this time before the exit of this ISR, another interrupt occurs. If the pending interrupt has a higher preemptive priority, this interrupt will be preempted, otherwise the pending interrupt will be served after this ISR return. This is called "chaining", because the pending ISR will immediately run after the exit of this ISR without returning to the original point when the first interrupt occurs.

I hope I have not confused anyone.