Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Not applicable
I'm using XMC4500 Relax Kit with XMC4500 F100K1024 processor.

I'm configuring PLL for 120 MHz frequency. I did everything perfectly and it worked. But suddenly, it stopped working. VCO stopped locking and VCO LOCK bit of PLLSTAT register remains zero.
What can be the reason for VCO LOCK to behave like this suddenly.

My source code:

  
/* Define the addresses for System Clock Registers*/
#define PLL_STAT (*(volatile unsigned long *) 0x50004710)
#define PLL_CON0 (*(volatile unsigned long *) 0x50004714)
#define PLL_CON1 (*(volatile unsigned long *) 0x50004718)
#define PLL_CON2 (*(volatile unsigned long *) 0x5000471C)
#define PLL_OSCHP (*(volatile unsigned long *) 0x50004704)
#define CLK_CLKCR (*(volatile unsigned long *) 0x5000460C)

/* Define the addresses for System Clock Configuration Register*/
#define SYS_CCR (*(volatile unsigned long *) 0xE000ED14)
#define CCR_RST 0x200

/* Define the PLL_STAT register bits*/
#define STAT_VCO_BYST 0x00000001
#define STAT_VCO_LOCK 0x00000004
#define STAT_VCO_PLLLV 0x00000080
#define STAT_VCO_PLLHV 0x00000100
#define STAT_VCO_PLLSP 0x00000200

/* Define the PLL_CON0 register bits*/
#define CON0_VCO_BYP 0x00000001
#define CON0_VCO_PWD 0x00000002
#define CON0_OSC_DIS 0x00000040
#define CON0_FIND_IS 0x00000010
#define CON0_PLL_PWD 0x00010000
#define CON0_RES_LD 0x00040000
#define CLK_EN_PLL 0x00010000

/* Define the Values for dividers*/
#define NDIV_SHIFT 8U
#define K2DIV_SHIFT 16U
#define PDIV_SHIFT 24U
#define NDIV_VAL 39U
#define K2DIV_VAL 3U


void config()
{
/* enable PLL */
PLL_CON0 &= ~(CON0_VCO_PWD | CON0_PLL_PWD);

/* Bypass the Main PLL */
PLL_CON0 |= CON0_VCO_BYP;

/* disconnect Oscillator from PLL */
PLL_CON0 |= CON0_FIND_IS;

/* Setup divider settings for main PLL */
PLL_CON1 |= ((NDIV_VAL << NDIV_SHIFT) | (K2DIV_VAL << K2DIV_SHIFT));

/* Set OSCDISCDIS */
PLL_CON0 |= CON0_OSC_DIS;

/* connect Oscillator to PLL */
PLL_CON0 &= ~ CON0_FIND_IS;

/* restart PLL Lock detection */
PLL_CON0 |= CON0_RES_LD;
while ((PLL_STAT & STAT_VCO_LOCK) == 0) //CODE GETS STUCK HERE FOREVER
{
/* wait for PLL Lock */
}

/* Disable bypass- put PLL clock back */
PLL_CON0 &= ~ CON0_VCO_BYP;
while ((PLL_STAT & STAT_VCO_BYST) != 0U)
{
/* wait for normal mode */
}

/* Switch system clock to PLL */
CLK_CLKCR |= CLK_EN_PLL;
}
0 Likes
1 Reply
lock attach
Attachments are accessible only for community members.
Travis
Employee
Employee
First solution authored Welcome! 500 replies posted
Hi,

Is there any chance that you can make use of Infineon DAVE4 as most of these clock initialization is taken care by the startup file. However I had attached the startup file for your reference.
0 Likes