Hi,
I would like to use the result interrupt and the source interrupt of VADC. But something is not correct.
Here is my code:
void VADC0_C0_0_IRQHandler(void)
{
int result = 0;
VADC->GLOBEFLAG |= 0x10000; // Clear source event interrupt indicate bit.
result = (VADC->GLOBRES & 0xFFFF) >> 2;
}
void VADC0_C0_1_IRQHandler(void)
{
int result = 0;
VADC->GLOBEFLAG |= 0x1000000; // Clear result event interrupt indicate bit.
//VADC->GLOBEFLAG |= 0x10000; // Clear source event interrupt indicate bit.
result = (VADC->GLOBRES & 0xFFFF) >> 2;
}
int main(void)
{
SCU_GENERAL->PASSWD = 0xC0; // Unlock protect bits. Block off.
SCU_CLK->CGATCLR0 = 0x1; // Disable gating (after disable gating, I can change VADC registers.
while((SCU_CLK->CLKCR) & 0x40000000); // Wait for VDDC to stabilize.
SHS0->SHSCFG = 0x8000; // Enable write access to ANOFF and AREF.
SHS0->SHSCFG &= ~(SHS_SHSCFG_ANOFF_Msk); // Toggle on converter.
*((int*)0x40010500) = 0x01; // Workaround to enable converter: ADC_AI.003. (only stepAA).
SHS0->SHSCFG |= 0x8800; // 0x8800 = write access + internal high
VADC->CLC = 0x00000000; // Enable the module clock.
VADC->GLOBCFG = 0x80000000; // Enable Start-Up calibration.
while ((SHS0->SHSCFG & SHS_SHSCFG_ANRDY_Msk) == 0); // Wait until converter is ready.
VADC->BRSSEL[0] = 0x89; // Enable inputs: 0, 3, 7.
VADC->BRSSEL[1] = 0x82; // Enable inputs: 1, 7.
VADC->GLOBICLASS[0] |= (0x01UL << VADC_GLOBICLASS_CMS_Pos); // Set 10 bit conversion.
VADC->GLOBICLASS[1] |= (0x01UL << VADC_GLOBICLASS_CMS_Pos); // Set 10 bit conversion.
VADC->GLOBRCR |= 0x80000000; // Service Request Generation Enable. Service request after all result events.
VADC->GLOBEVNP |= 0x10000; // Serivce line 1.
//VADC->BRSMR |= 0x8; // Source interrupt. // I uncomment this to the purpose of demonstration.
//VADC->GLOBEVNP |= 0x1; // Service line 1.
// Set interrupt channel.
NVIC_SetPriority(VADC0_C0_0_IRQn, 3);
NVIC_EnableIRQ(VADC0_C0_0_IRQn);
NVIC_SetPriority(VADC0_C0_1_IRQn, 3);
NVIC_EnableIRQ(VADC0_C0_1_IRQn);
// Start new conversion.
VADC->BRSMR |= 0x211; // Requests are issued, autoscan enable (automatically generate next load event), generate load event.
while(1)
{
}
}
The result event works properly, but the source event not.
My problems with source vent:
- The source event is always active. Even if the ENSI bit is 0 in BRSMR register, the interrupt happens. If I set ENSI to 1, then interrupt happens as well.
- If I change the SEV0NP bitfield from 0 to 1 in GLOBEVNP register, then the interrupt stay on SR0 (the bitfield changes in DAVE).
Could somebody help me?
