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Hi all,

I came across yet another confusing feature that I was hoping this community would help me clarify 🙂 Quoting the reference manual,:

While bitfield BNDSELX = 0000B, bitfields BNDSELU and BNDSELL select the valid upper/lower boundary value either from the group-specific boundary register GxBOUND (x = 0 - 3) or from the global boundary register GLOBBOUND. The group boundary register can be selected for each channel f the respective group, the global boundary register can be selected by each available channel.
Otherwise, the compare values are taken from result registers, where bitfield BNDSELX
selects the upper boundary value (GxRES1 … GxRES15), the concatenated bitfields BNDSELU||BNDSELL select the lower boundary value (GxRES0 … GxRES15).


Whereas the operation of the limit checking mechanism is more or less straightforward, the boundary value selection is confusing. Firstly, I was not able to find a bitfield called BNDSELX - hence I assumed (since it's given as a 4 bit field) that it's a combination of the two boundary registers, namely BNDSELU and BNDSELL, represented as one. But if both fields are set to 00B, then the following condition occurs:

1800.attach

The second part of this statement confused me even further. What I thought was happening is that the boundary values were set during the initialization phase and the compare values were simply compared against those pre-defined entries. I am using XMC4400 kit and reading the corresponding reference manual.

Regards and thank you in advance,
Andrey
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3 Replies
Travis
Employee
Employee
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Hi,

Whereas the operation of the limit checking mechanism is more or less straightforward, the boundary value selection is confusing. Firstly, I was not able to find a bitfield called BNDSELX - hence I assumed (since it's given as a 4 bit field) that it's a combination of the two boundary registers, namely BNDSELU and BNDSELL, represented as one.

So sorry for the confusion, BNDSELX is referring to the combination of both BNDSELU and BNDSELL.

But if both fields are set to 00B, then the following condition occurs

I am not sure if this is a typo, as both boundary (Upper and Lower) shares the same value does not make any sense to me too. Let me check on this.
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Hi Travis,

First off, let me apologize - when I said "yet another confusing feature..." I was referring to a general trend of me misunderstanding parts of the reference manual, and not necessarily due to lacking clarity 🙂

That being said, thank you for the quick reply and clarification! To summarize the idea that has formed in my mind after reading the manual and playing around with some code - the boundary values written in corresponding registers are used as-is in either limit checking or fast compare modes (i.e. they are not combined, only added and subtracted to and from compare value in fast compare mode). Hopefully this is accurate and can help anyone should they face the same question.

Regards,
Andrey
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funkyluke
Level 2
Level 2
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I know this is an old thread, but I might shed some light on this:
BNDSELx is defined for the XMC1200 as the bitfield at CHCTR[15:12], for the XMC4000 these bits are defined as "reserved".
The Operation is defined here: https://www.infineon.com/dgdl/Infineon-VADC-XMC1200_XMC1300-AP32304-AN-v01_10-EN.pdf
IDK if the XMC4000 just doesn't have this feature or if the documentation is faulty. It is, however NOT identical to BNDSELU & BNDSELL, as Travis suggested.
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