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Hi all,

I am trying to configure the VADC module to operate in Fast Compare Mode to perform some actions depending on whether the signal is above or below the compare value. In other words, I want the channel events to be generated on both transitions - i.e. when the input signal drops below the compare value or rises above it. However, the corresponding flag is not being set! The following are configuration code snippets. Note that whenever I set the corresponding flag manually, the interrupt is triggered and the actions are performed as they should.

Initialization Code
void TestCase4Routine_BoundaryCheckWithFastCompare() {
/* VADC Initialization */
XMC_VADC_GLOBAL_Init(VADC, &global_config);

/* Set up boundary values in group configuration */
XMC_VADC_GROUP_Init(group_identifier, &group_config);

XMC_VADC_GROUP_QueueInit(group_identifier, &queue_config);

XMC_VADC_GROUP_ChannelInit(group_identifier, (uint32_t)CHANNEL1_NUMBER, &channel1_config_alternative);

XMC_VADC_GROUP_ResultInit(group_identifier, (uint32_t)RESULT_REGISTER1_NUMBER, &result1_config_alternative);


XMC_VADC_GROUP_SetResultFastCompareValue(group_identifier, (uint32_t)RESULT_REGISTER1_NUMBER, (XMC_VADC_RESULT_SIZE_t) FAST_COMPARE_VAL);


// Result register is set in channel_config data structure
XMC_VADC_GROUP_QueueInsertChannel(group_identifier, queue_entry_config1);

// Event flag is not set for some reason - i.e. event is not happening
XMC_VADC_GROUP_ChannelSetEventInterruptNode(group_identifier, (uint32_t)CHANNEL1_NUMBER, XMC_VADC_SR_GROUP_SR0);

NVIC_SetPriority(VADC0_G0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),63,0));
/* End VADC Initialization */

Channel Configuration Structure
XMC_VADC_CHANNEL_CONFIG_t channel1_config_alternative = {
.lower_boundary_select = XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0,
.upper_boundary_select = XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1,
.invert_boundary_flag_ch0 = false,
.event_gen_criteria = XMC_VADC_CHANNEL_EVGEN_ALWAYS, /* When switches to either level in FCM */
.sync_conversion = false,
.alternate_reference = XMC_VADC_CHANNEL_REF_INTREF,
.result_reg_number = (uint8_t)RESULT_REGISTER1_NUMBER,
.use_global_result = false,
.result_alignment = XMC_VADC_RESULT_ALIGN_RIGHT,
.broken_wire_detect_channel = XMC_VADC_CHANNEL_BWDCH_VAGND,
.broken_wire_detect = false,
.channel_priority = true, /* Boolean Value */
.alias_channel = (uint8_t) XMC_VADC_CHANNEL_ALIAS_DISABLED

Queue Configuration
XMC_VADC_QUEUE_CONFIG_t queue_config = {
.conv_start_mode = XMC_VADC_STARTMODE_WFS,
.req_src_priority = XMC_VADC_GROUP_RS_PRIORITY_3, /* Highest priority */
.src_specific_result_reg = false,
.trigger_signal = XMC_VADC_REQ_TR_G, /* Trigger G is not connected to any input */
.gate_signal = XMC_VADC_REQ_GT_A, /* Connected to CCU40 which is not used */
.timer_mode = false,
.external_trigger = false
XMC_VADC_QUEUE_ENTRY_t queue_entry_config1 = {
.channel_num = CHANNEL1_NUMBER,
.refill_needed = true,
.generate_interrupt = false,
.external_trigger = false

My assumption is that when one wants to use the Fast Compare Mode, the compare value is configured in the RESULT bitfield of the corresponding register, and the input value is compared against it, i.e. only one register is needed.

Thank you all in advance.
2 Replies
Not applicable
Sometimes it takes asking a question to figure out the problem almost right away. The culprit was the Wait-for-read mode that I have set to true. Effectively, the result was never read out, which meant that there were no new conversions occurring and, consequently, no transitions from below to above or channel events. Disabling the WFR mode has fixed the problem.

Thank you all for visiting the question page.

Edit: Here is a relevant snippet from the reference manual that hasn't caught my attention previously, unfortunately. It is regarding the question of the number of registers needed for the Fast Compare Mode.
For standard conversions, result values are available in bitfield RESULT. Conversions in Fast Compare Mode use bitfield RESULT for the reference value, so the result of the operation is stored in bit FCR.
First solution authored Welcome! 500 replies posted
Very GOOD answer.