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Level 4
Level 4
Good day,

Please verify my understanding how VADC arbitration works:

Assuming System Clock fADC=120MHz or Tsys=8,(3) nanoSec.
/*8,(3) = 8,333333333333333...*/
Analog Clock will be fADCI=120MHz/4=30MHz corresponds Tadc=33,(3) nanoSec respectively.

Shortest possible arbitration round takes 33,(3)*4=133,(3) nanoSec.
(I suppose decision done in the end of the round.)

Standard 12-bit ADC takes 550 nanoSec or 16,5*Tadc.

A) In case I want use external trigger for sampling, from my Triggering Signal
and time when S/H amplifier of ADC start to work, pass:

- fixed 133,(3) nanoSec for arbitration + up to 8,(3) nanoSec due fADC uncertainity
(In case arbiter running "on request");

- fixed 133,(3) nanoSec for arbitration + up to 133,(3) nanoSec due "uncomplete" arbitration uncertainity
(In case arbiter running "permanently").

But in first mode synchronized conversion for several VADC groups not possible unfortunately.
So in case I need use 2 or more VADC groups, I will face 133,(3) nanoSec delay and uncerainity.

B) In case I use VADC with Background Source, it's working like auto-generator.
Say, conversion starts at the end of arbitration round and takes 16,5*Tadc, or 550nanoSec.
So next conversion initiated only 0,5*Tadc from arbitration round beginning. As far it is
therefore incomplete, next conversion starts only after next, complete round only, o.w.
(16,5+3,5+4=24)Tadc. Then story repeats. So we will have sampling period of 24*33,(3)=800nanoSec
(instead of 550nanoSec when conversion actually ends) or 1,25MHz sampling frequency.

So if option exist to disable arbitration completely, say in case one Signal Source
already choosen for ADC? IMHO it will be extremly usefull in some cases:)

Best regards,
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