I'm using P2G kit to develop a UART communication. I use FIFO buffer to transmit and receive UART Interrupt mode.
Ex:
UART_Receive(&UART_0, uart_instance.payloadISR, sizeof(uart_instance.payloadISR)); (payload is 5 bytes length). FIFO buffer 16 bytes.
I see in the comment of UART_Receive that FIFO buffer will be flushed after I receive full of my desire bytes (here is 5 bytes). But in practice I see that buffer is not flushed as expectec.
For example, I receive 5 bytes, communication is successful as expected. But when I receive 4 bytes, and next time sender send another msg with 5 bytes, 1 byte in the 2nd msg will be fill in the missing one in the 1st msg. Yeah it's ok at this part. But I expect that other 4 bytes remain in 2nd msg will be flushed, so when the 3rd msg with full 5 bytes arrive, it will not occur the situation like the 1st and 2nd msg. But I see that 3rd is still suffer that problem, and other msg continue the same, until the nth msg, everything is ok, 5 bytes receive correctly again (I do not know when the nth msg arrive, sometime it 4th, 8th,... it's not stable). Hope to hear the answer from you guys. Thanks.
