Timer-based start of UART transmission.

[rst]

Hi!

I need to implement the timer-based start of UART transmission.
Format: 24-N-1 (24 data bits, 1 stop bit, no parity).
USIC initialize as: SCTR.WLE == 16bit, SCTR.FLE == 24 bits.
Without synchronization with the timer, the transmission works is ok. See picture below:

But if you allow the start of the transfer from the signal DX2T, then on each edge of DX2T
not a whole frame is transmitted, but only word by word. See picture below:

I use:
DXCR[2] = 1 << 10 | 1 << 4 | input << 0;
TCSR.TDVTR = 1;

Is it possible to start USIC transmissions from timer events at all? And How?
Thanks in advance for the help!

[jferreira]

Hi,

The documentation states "A transfer trigger logic supports data word transfers related to events, e.g. timer based or related to an input pin"
Did you try using the FIFO and triggering on rising and falling edge?

Regards,
Jesus

[rst]

jferreira wrote:
The documentation states "A transfer trigger logic supports data word transfers related to events, e.g. timer based or related to an input pin"
Did you try using the FIFO and triggering on rising and falling edge?

Initially I tried to load in FIFO two words (16 bits + 8 bits or 16 bits + 16 bits) and trigger the transfer using single edge (rising or falling). Result - second picture.
Then I tried to triggers using both edges (rising or falling). The result was the same (as if only single edge was used).
I got an opinion that the event triggers the coping of only a single word (16 bit) from frame (from FIFO) to the shift register of the transmitter.
And the transfer of the remainder of frame occurs as if no another words have been loaded to the transmitter's FIFO.
The remaining bits of the frame have been filled the passive level (SCTR.PDL).

PS: I need to perform two tasks (transmit from one CPU to another CPU):
1. Transmit 24 bits of data;
2. Simultaneously transmit the synchronization signal (by position of the begin or end of frame).
This must be done accurately, without delay. Therefore, CPU or DMA can not be used for start of transfer.
It is desirable to do this using only single timer's event, since there are not enough free compare-registers in the CCU for generate a second timer event (rest compare-registers are used for other purposes).