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Not applicable
Here is the code for a simple DMX Transmitter:

#include
#include "GPIO.h"

/* USIC : FIFO DPTR & SIZE MASK and POS Values */
#define USIC_CH_TBCTR_DPTRSIZE_Pos (0U)
#define USIC_CH_TBCTR_DPTRSIZE_Msk (0x0700003FU << USIC_CH_TBCTR_DPTRSIZE_Pos)
#define USIC_CH_RBCTR_DPTRSIZE_Pos (0U)
#define USIC_CH_RBCTR_DPTRSIZE_Msk (0x0700003FU << USIC_CH_RBCTR_DPTRSIZE_Pos)

//#define _19200_Baud
//#define _115000_Baud
#define _256000_Baud

#ifdef _19200_Baud
// 19.2kbd @32MHz
#define FDR_STEP 472
#define BRG_PDIV 44
#define BRG_DCTQ 16
#define BRG_PCTQ 0
#endif

#ifdef _115000_Baud
// 115kbd @32MHz
#define FDR_STEP 465
#define BRG_PDIV 5
#define BRG_DCTQ 20
#define BRG_PCTQ 0
#endif

#ifdef _256000_Baud
// 256kbd @32MHz
#define FDR_STEP 467
#define BRG_PDIV 2
#define BRG_DCTQ 18
#define BRG_PCTQ 0
#endif


int main(void){

uint32_t i = 0;


//• Changing the MCLK and PCLK frequency via CLKCR register
//FDIV, IDIV, PCLKSEL, RTCLKSEL = 0x3FF00100 = PCLK = MCLK, MCLK = 32MHz
// 0x3FF00200 = PCLK = MCLK, MCLK = 16MHz
// 0x3FF10100 = PCLK = 2xMCLK, MCLK = 32MHz
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CLKCR = 0x3FF10100;
while((SCU_CLK->CLKCR)&0x40000000UL);
SCU_GENERAL->PASSWD = 0x000000C3UL;

//USIC Configuration Disable the USIC0 clock gating
SCU_GENERAL->PASSWD = 0x000000C0UL;
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_USIC0_Pos);
while ((SCU_CLK->CLKCR)&(SCU_CLK_CLKCR_VDDC2LOW_Msk)){;}
SCU_GENERAL->PASSWD = 0x000000C3UL;
//Disable UART mode before configuring all USIC registers to avoid unintended edges
USIC0_CH1->CCR &= ~( ((uint32_t)(0x02U & USIC_CH_CCR_MODE_Msk)));

//Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel
//modes for the different device operating modes.
USIC0_CH1->KSCFG |= (1 << USIC_CH_KSCFG_MODEN_Pos) | (1<< USIC_CH_KSCFG_BPMODEN_Pos); //Kernel State Configuration Register
//Fractional Divider mode selected
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_DM_Msk, USIC_CH_FDR_DM_Pos, 2 );//ok
//Step Value
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_STEP_Msk, USIC_CH_FDR_STEP_Pos, FDR_STEP);
//PreDivider for CTQ, PCTQ = 0, Denominator for CTQ, DCTQ = 16
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PCTQ_Msk, USIC_CH_BRG_PCTQ_Pos, BRG_PCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_DCTQ_Msk, USIC_CH_BRG_DCTQ_Pos, BRG_DCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PDIV_Msk, USIC_CH_BRG_PDIV_Pos, BRG_PDIV);
//Configuration of USIC Shift Control
//Transmit/Receive LSB first is selected, Transmission Mode (TRM) = 1, Passive Data Level (PDL) = 1
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_PDL_Msk, USIC_CH_SCTR_PDL_Pos, 1);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_TRM_Msk, USIC_CH_SCTR_TRM_Pos, 1);
//Set Word Length (WLE) & FRame Length (FLE)
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, 7);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_WLE_Msk, USIC_CH_SCTR_WLE_Pos, 7);
//Configuration of USIC Transmit Control/Status Register
//TBUF Data Enable (TDEN) = 1, TBUF Data Single Shot Node (TDSSM) = 1
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDEN_Msk, USIC_CH_TCSR_TDEN_Pos, 1);
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDSSM_Msk, USIC_CH_TCSR_TDSSM_Pos, 1);
//Configuration of Protocol Control Register
//Sample Mode (SMD) = 1, Stop Bit is selected, Sample Point (SP) = 2, Pulse Length (PL) = 0
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SMD_Msk, USIC_CH_PCR_ASCMode_SMD_Pos, 1);
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_STPB_Msk, USIC_CH_PCR_ASCMode_STPB_Pos, 1); //2 Stopbits
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SP_Msk, USIC_CH_PCR_ASCMode_SP_Pos, 6);
//TBIF is set to simplify polling
WR_REG(USIC0_CH1->PSR_ASCMode, USIC_CH_PSR_TBIF_Msk, USIC_CH_PSR_TBIF_Pos, 1);
//Configuration of Transmitter Buffer Control Register
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_LIMIT_Msk, USIC_CH_TBCTR_LIMIT_Pos, 0);
//Configuration of Channel Control Register
//Parity generation is disabled
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 2);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_PM_Msk, USIC_CH_CCR_PM_Pos, 0);
//Data Pointer & Buffer Size for Transmitter Buffer Control - DPTR = 64, Size = 6
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos, 0x06000040);

while(1){
//Break 176µs
P1_2_set_mode(OUTPUT_PP_GP);

P1_2_reset();
i = 0;
do{
i++;
}while(i < 425);
//Mark After Break 12µs
P1_2_set();
i = 0;
do{
i++;
}while(i < 42);

// Configuration of TX Pin 1.2 based on User configuration
P1_2_set_mode(OUTPUT_PP_AF7);
//Startbyte
USIC0_CH1->IN[0] = 0;
//Channel 1
USIC0_CH1->IN[0] = 10;
//Channel 2
USIC0_CH1->IN[0] = 100;
//Channel 3
USIC0_CH1->IN[0] = 200;
}

//return 0;
}
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1 Reply
Not applicable
Is this a working code?
That would be great!!
Is sure benefit the community here..

rgds,
Rou
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