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Not applicable
Hi,

I've configured SPI master in DAVE3. Is this a good way to transfer a byte?
RIF should clear in the user software?


#include //Declarations from DAVE3 Code Generation (includes SFR declaration)

int main(void)
{
// status_t status; // Declaration of return variable for DAVE3 APIs (toggle comment if required)
uint16_t Data = 0;

DAVE_Init(); // Initialization of DAVE Apps


Data = 0x81;

const SPI001_HandleType* Handle = &SPI001_Handle0;
USIC_CH_TypeDef* USICRegs = Handle->USICRegs;
USICRegs->TBUF[0] = Data;

while (!(USICRegs->PSR & USIC_CH_PSR_RIF_Msk)) ; //wait for RIF to set

while(1)
{
}
return 0;
}
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10 Replies
Travis
Employee
Employee
First like received
Hi jsmith65,

There are many low level driver example using DAVE4 at the below link. This should be able to assist you faster.


http://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-ar...
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Not applicable
Thanks for your response.

But if somebody can answer my original question please answer it.
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AngelB
Employee
Employee
Hi jsmith65,

every flag from the protocol status register (PSR) needs to be cleared by software always writing 1 to the respective position of the PSCR register..

Regarding your implementation:

RIF(Receiver interrupt flag), is indicating the reception of the last data bit of a data word if this word is not also the first one.
In your case,one word data frame(first data word of a frame) is being sent, so you should check AIF(Alternative receive interrupt flag) which is indicating the reception of the first word in a frame.

Please,also take in account that in some devices there is an Errata in hardware that may change this described behavior by setting RIF instead of AIF after receiving the first word of a frame (for example USIC_AI.007 in XMC4500 AC step).

So, my recommendation, and which will work regardless the device used is checking both flags, if one of the two flags is set data has been completely sent:


#include //Declarations from DAVE3 Code Generation (includes SFR declaration)

int main(void)
{
// status_t status; // Declaration of return variable for DAVE3 APIs (toggle comment if required)
uint16_t Data = 0;

DAVE_Init(); // Initialization of DAVE Apps


Data = 0x81;

const SPI001_HandleType* Handle = &SPI001_Handle0;
USIC_CH_TypeDef* USICRegs = Handle->USICRegs;
USICRegs->TBUF[0] = Data;

while (!((USICRegs->PSR & USIC_CH_PSR_RIF_Msk) || (USICRegs->PSR & USIC_CH_PSR_AIF_Msk))) ; //wait for RIF and AIF to set

while(1)
{
}
return 0;
}

Best regards,
Angel
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Not applicable
PSCR.bit need to be cleared?

Consider the following scenario:

first word
wait for transmit finished using TSIF
clearing TSIF by writing PSCR.TSIF=1

second word (here PSCR.TSIF=1?)
wait for transmit finished using TSIF
clearing TSIF by writing PSCR.TSIF=1 (how the chip will identify the change when it is still 1?)
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AngelB
Employee
Employee
Hi jsmith65,

PSR.bit need to be cleared by using PSCR.bit.

PSR register is the one that contains the status flags and this is not cleared by hardware.

PSCR register is the one that erases the status flag in PSR. This register is cleared just after being written.


In your scenario:

first word
wait for transmit finished using TSIF //using PSR.TSIF. Now PSR.TSIF= 1
clearing TSIF by writing PSCR.TSIF=1 // Right, after doing this PSR.TSIF =0

second word (here PSCR.TSIF=1?) //No. Here PCSR.TSIF=0. PSCR is just clearing the flag in PSR and PSCR becomes 0 just after. Here after the word has been sent PSR.TSIF=1.
wait for transmit finished using TSIF //using PSR.TSIF. Now PSR.TSIF= 1
clearing TSIF by writing PSCR.TSIF=1 (how the chip will identify the change when it is still 1?) //After doing this PSR.TSIF = 0

BR,
Angel
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Not applicable
The behaviour is same for CCU40.GCSC?
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Not applicable
Assume I have a spi transmit code with WLE=8, FLE=8, TBCTR.DPTR=0, TBCTR.SIZE=32

When I fill the IN array my app will generate 32 frame?

...
USIC0_CH1->CCR = 0x00000001;
for (int i=0; i<31; i++)
USIC0_CH1->IN = data;
...
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chismo
Employee
Employee
First like received
Hello,

Yes, since frame size is defined as 8-bit (register bit field SCTR.FLE=7), each word written to the FIFO will be taken as one frame.

If the intention is to send a single frame consisting of 32 bytes, FLE has to programmed to the maximum value of 63, which selects infinite frame length.
In this case, an explicit frame end has to be indicated to the USIC channel.
For example, by writing 1 to the bit field TCSR.EOF before writing the last word of the frame to the FIFO.

Regards,
Min Wei
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Not applicable
Which event will trigger 'get the next item from fifo' ?
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chismo
Employee
Employee
First like received
This will be the transmit buffer event, which is indicated by the PSR.TBIF flag.
With this event, the previous data in the internal TBUF has been loaded to the shift register.
Therefore, a new data from FIFO (or standard buffer if FIFO is not used) can be now loaded into the TBUF.
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