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User8570
Level 3
Level 3
Hello

I am trying to read/write data from a EEPROM chip. (25AA02UID). Checking the clock signal on the scope there is a silence period between two SPI write operations, The chip needs the clock signal be right away between the Command (Write/Read) and the address.


I am using the following code:

EnableStartOfFrame(SPI001_Handle0);

SPI001_ClearFlag(&SPI001_Handle0,SPI001_RECV_IND_FLAG);
SPI001_ClearFlag(&SPI001_Handle0,SPI001_ALT_RECV_IND_FLAG);

Data = 0x03;
/* Send read page command */
SPI001_WriteData(&SPI001_Handle0,&Data,SPI001_STANDARD);

Data = 0x05;
/* Send read page command */
SPI001_WriteData(&SPI001_Handle0,&Data,SPI001_STANDARD);


Data = 0x00;
/* Send read page command */
SPI001_WriteData(&SPI001_Handle0,&Data,SPI001_STANDARD);


//wait for dummy to be received
do
{
Status1 = SPI001_GetFlagStatus(&SPI001_Handle0,SPI001_RECV_IND_FLAG);
Status2 = SPI001_GetFlagStatus(&SPI001_Handle0,SPI001_ALT_RECV_IND_FLAG);
}while(!((Status1 == SPI001_SET) || (Status2 == SPI001_SET)));


SPI001_ReadData(&SPI001_Handle0,&tmp); // dummy read
EnableEndOfFrame(SPI001_Handle0);


Wondering if I am missing something on the SPI configuration
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9 Replies
Not applicable
Hi,

What is the frame length you have configured?
You have to set it to 64 which is equal to unlimited data frame or it will have a small delay between words/frame.
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User8570
Level 3
Level 3
Jackson

I changed the frame length to 64 and not luck. Anything else I can change? I am attaching the SPI001 App Config Page and the scope readings.
781.attach782.attach
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Not applicable
Hi,

The interframe delay looks more than what I have expected.
I will try to reproduce at my side to see what could be the possible error.
Meanwhile, could you try to writing to the FIFO directly instead of using the APIs provided?
I suspect it could be the API overhead that cause the delay.
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Not applicable
Hi,

I just tried and it is indeed having a big gap in between data to data.
So what I do is increase the FIFO size and place the data directly into the FIFO register instead of using the APIs.
Then it turns out as expected, no more gap in between data.
Perhaps you can give it a try..
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User8570
Level 3
Level 3
Jason

Should I remove the SPI001App? or keep it with a bigger FIFO size such as 16? Then how do I write to the fifo directly?
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User8570
Level 3
Level 3
Jason

The SPI Write data function contains:

bool SPI001_WriteData
(
const SPI001_HandleType* Handle,
const uint16_t* DataPtr,
SPI001_TransmitMode TrMode
)
{
bool Result = (bool)FALSE;
uint32_t HpcenNew = 0x00U;
uint8_t TbufIndex = 0x00U;
USIC_CH_TypeDef* USICRegs = Handle->USICRegs;
/* <<>>*/
HpcenNew = ((uint32_t)((uint32_t)TrMode & SPI001_TRMODE_Msk) >> (uint32_t)3);

if(USIC_IsTxFIFOfull(USICRegs))
{
Result = (bool)FALSE;
}
else
{
USICRegs->CCR &= (~USIC_CH_CCR_HPCEN_Msk);
USICRegs->CCR |= ((HpcenNew << USIC_CH_CCR_HPCEN_Pos) & \
USIC_CH_CCR_HPCEN_Msk);
TbufIndex = (uint8_t)((uint8_t)TrMode & (uint8_t)SPI001_TBUFINDEX_Msk);
USICRegs->IN[TbufIndex] = *DataPtr;
Result = (bool)TRUE;
}

return Result;
}


Should I use only this function to write on the FIFO: USICRegs->IN[TbufIndex] = *DataPtr; ?

Not sure if I need to setup the USICRegs for that SPI Handle first?

Please advise.

Thanks
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Not applicable
Hi,

You can still keep the SPI001 app.
Just need to increase the FIFO buffer size.
I don't think you can use 'USICRegs' unless you setup the handler, so the easiest way is use the USIC channel directly.
For example you are using USIC 0 Channel 1, then you can write USIC0_CH1->IN[0] = data;
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User8570
Level 3
Level 3
Jackson

I was able to generate consecutive writes but I can't read. I am using USIC2 CHannel 0, Can you suggest me also a technique to do a read operation after a write without any delay?

Thanks
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Not applicable
Hi,

Can you explain what you can't read?
Is the read value wrong or the module did not received any data?
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