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Jul 29, 2013
01:40 AM
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Jul 29, 2013
01:40 AM
Hi,
I tried to configure a XMC1300 to work in SPI-Slave-Mode by setting the USIC-registers in this way:
(since I just want to receive data, I didn't initialise the data output pin)
Unfortunately, I can't receive the data I'm sending with a PIC24F by Microchip (Master)...
I watched the USIC-registers while debugging and after the PIC had sent 0xAA they looked like this:
http://s14.directupload.net/file/d/3331/tzwxadmk_jpg.htm
according to the RBUFSR (RBUFSR01) register, a "protocol related error" occured but what's that supposed to mean?
Maybe I forget something in my USIC settings...
Can anybody help me?
I tried to configure a XMC1300 to work in SPI-Slave-Mode by setting the USIC-registers in this way:
(since I just want to receive data, I didn't initialise the data output pin)
#include
void USIC0_Init(void)
{
//Kernel State Configuration Register - Module Enable + Bit Protection for MODEN
USIC0_CH1->KSCFG |= (1 << USIC_CH_KSCFG_MODEN_Pos) | (1 << USIC_CH_KSCFG_BPMODEN_Pos);
//Configuration of USIC Input Stage
WR_REG(USIC0_CH1->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos, 1); //MOSI: P1.2
WR_REG(USIC0_CH1->DX0CR, USIC_CH_DX0CR_INSW_Msk, USIC_CH_DX0CR_INSW_Pos, 1);
WR_REG(USIC0_CH1->DX1CR, USIC_CH_DX1CR_DSEL_Msk, USIC_CH_DX1CR_DSEL_Pos, 1); //SCKL: P0.8
WR_REG(USIC0_CH1->DX1CR, USIC_CH_DX1CR_INSW_Msk, USIC_CH_DX1CR_INSW_Pos, 1);
WR_REG(USIC0_CH1->DX2CR, USIC_CH_DX2CR_DSEL_Msk, USIC_CH_DX2CR_DSEL_Pos, 1); //SS: P0.9
WR_REG(USIC0_CH1->DX2CR, USIC_CH_DX2CR_INSW_Msk, USIC_CH_DX2CR_INSW_Pos, 1);
//Configuration of USIC Shift Control
//Transmission Mode (TRM) = 1
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_TRM_Msk, USIC_CH_SCTR_TRM_Pos, 1);
//Configuration of Channel Control Register
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 1);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_AIEN_Msk, USIC_CH_CCR_AIEN_Pos, 1);
}
int main(void)
{
uint32_t buffer = 0;
while(1)
{
buffer = USIC0_CH1->RBUF0;
//buffer = USIC0_CH1->RBUF1;
}
return 0;
}
Unfortunately, I can't receive the data I'm sending with a PIC24F by Microchip (Master)...
I watched the USIC-registers while debugging and after the PIC had sent 0xAA they looked like this:
http://s14.directupload.net/file/d/3331/tzwxadmk_jpg.htm
according to the RBUFSR (RBUFSR01) register, a "protocol related error" occured but what's that supposed to mean?
Maybe I forget something in my USIC settings...
Can anybody help me?
- Tags:
- IFX
3 Replies
Not applicable
Jul 29, 2013
08:57 PM
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Jul 29, 2013
08:57 PM
Hi TomTurbo,
From your initialization, everything looks alright.
Did you disable the clock gating of the USIC module?
You should have something like the below code before calling USIC0_Init();
rgds,
Rou
From your initialization, everything looks alright.
Did you disable the clock gating of the USIC module?
You should have something like the below code before calling USIC0_Init();
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CGATCLR0 |= 0x00000008; // disable USIC clock gating
while((SCU_CLK->CLKCR)&0x40000000UL);
SCU_GENERAL->PASSWD = 0x000000C3UL;
USIC0_Init();
rgds,
Rou
Not applicable
Jul 30, 2013
01:16 AM
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Jul 30, 2013
01:16 AM
Hi Rou,
thanks for the hint, I forget those clock seetings...the XMC received something but the errors are still the same:

Regardless of what I'm sending, the values of RBUF and RBUF0 are always 0x1:confused:
thanks for the hint, I forget those clock seetings...the XMC received something but the errors are still the same:
Regardless of what I'm sending, the values of RBUF and RBUF0 are always 0x1:confused:
Not applicable
Aug 02, 2013
01:04 AM
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Aug 02, 2013
01:04 AM
Hi TomTurbo,
Instead of reading directly from RBUF0 or RBUF1, I would suggest you to read from RBUF only.
Perhaps something like this:
rgds,
Rou
Instead of reading directly from RBUF0 or RBUF1, I would suggest you to read from RBUF only.
Perhaps something like this:
while((USIC0_CH1->PSR_SSCMode & USIC_CH_PSR_SSCMode_AIF_Msk)==0); // Wait until alt. received flag is set
USIC0_CH1->PSCR |= USIC_CH_PSR_SSCMode_AIF_Msk; // Clear flag
buffer = USIC0_CH1->RBUF;
rgds,
Rou