SCG Slope Value

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User17106
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Hi,

I am using the XMC4400 and the CSG unit. Initially, I used the DAVE-APP to configure it:

 

User17106_0-1656676404090.png

When I configure slope = 200mV/us, the value given to the CSG registers are:

CSG0.SC = MCLK (120MHz)
CSG0SC.FPD = ENABLED
CSG0.SC.PSV = /1

for 30MHZ clock, and:

CSG0.SC.PSWM =  #b10    (64bit window)
CSG0.SC.GCFG = #b00       (x1)
CSG0.PC =31

Is this correct?

How is this calculated?

regards.

 

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Alakananda_BG
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Hi @User17106 ,

It is true that slope voltage is not available on a pin, but it can be seen indirectly.

You can try to replicate the example project provided on COM_SLOPE_GEN app and monitor the HRPWM OUT pin with an oscilloscope probe.

You can find the  step by step guide here : open the "help" on the CSG_App and select "Usage" 

Regards,

 

Alakananda

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Alakananda_BG
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Hi @User17106 ,

  • We have slope control unit which handles several available slope generation modes.
  • We have a step control unit which generates clock for the slope control unit.
  • Inside the step control block it has 2 dedicated clock prescalers - one fixed prescaler and one programmable and a clock pulse swallower.
  • Inside the Step Control block there is also a pulse swallow unit. This unit contains a dedicated 6 bit compare value, CSGyPC.PSWV, that can be programmed accordingly with the number of pulses that need to be swallowed to achieve the wanted step clock distribution.

Below figure shows the operation of this mechanism when the pulse swallow value is set to 4 (CSGyPC.PSWV = 04H) and CSGySC.PSWM is set to 00B (16 clock cycle window mode).
Notice that the pulse swallow counter is a bit reverse counter, which means that the swallowed pulses are going to be distributed evenly over a 16 clock cycle period (clock at the output of the programmable prescaler, psc_out_clock).
With this mechanism one is able to generate intermediate slope decay values between
two different clock division ratios.
Due to the fact that the pulse swallow counter operates with the prescaler output clock, when a external signal is used as start & clear for the prescaler, the pulse swallow counter is also cleared.

Alakananda_BG_0-1657001445097.png

 

You can refer to the reference manual attached below for more information.

Regards,

 

 

 

Alakananda
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There is no formula in the manual on how to calculate the slope value.

According to the manual and my calculations, with the configuration given by the DAVE APP, the slope value is not 200mV/us but four times less than 50mV/us.

I think to get the slope value of 200mV/us it is required to change the value of CSG0.SC.GCFG = #b10 to have a gain of x4. Could there be a bug here?

There is no way to check the value of this slope as it is an internal signal.

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Alakananda_BG
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50 likes received 250 sign-ins 250 replies posted

Hi @User17106 ,

It is true that slope voltage is not available on a pin, but it can be seen indirectly.

You can try to replicate the example project provided on COM_SLOPE_GEN app and monitor the HRPWM OUT pin with an oscilloscope probe.

You can find the  step by step guide here : open the "help" on the CSG_App and select "Usage" 

Regards,

 

Alakananda
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