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User12789
Level 3
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The CCU8 timers on the XMC4400 and 4700 have a strange quirk when in center-aligned PWM mode.

When setting the duty cycle to 0%, the reference manual says "generating a 0% duty cycle signal is always possible by setting a value in the compare register bigger than the one programmed into the period register". The quirk affects how the complementary output is generated in this case.

If you program the compare register with the value in the period register + 1 things work as expected, and the complementary output appears as a 100% duty cycle signal. If you set it to anything larger, such as period register + 2, the complementary output appears as either a glitch or as a 0% duty cycle some of the time. This is not consistent--sometimes the complementary output is 100% (as expected) and sometimes it just glitches or stays low.

The manual should say "generating a 0% duty cycle signal is always possible by setting a value in the compare register to the one programmed into the period register + 1". Setting it to "a value in the compare register bigger than the one programmed into the period register" will cause problems in the complementary output.

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ncbs
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Hi @User12789,

Please find the project attached used to test the same. This project has been created for XMC4700 relax kit. The project has a single CCU8 slice unit, and out1 and out2 have been connected to two GPIOS (P5.10 and P0.1). The outputs were observed for a various range of frequencies from Hz to kHz range. 

The period register value is kept at 16000 and the compare register value was kept at 20000 (which is not period value + 1). No glitches were observed in either out1(st) or out2(inverted st1). 

Hence, the statement present in the reference manual holds true - "generating a 0% duty cycle signal is always possible by setting a value in the compare register bigger than the one programmed into the period register". 

Regards,
Nikhil

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ncbs
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Hi @User12789,

Can you share the waveforms for the normal and the "quirky" behavior observed?

Also, I see that you have observed this on XMC4400 and 4700. Did you observe this on other XMC devices? 

Can you share the project used for testing the same here?

Regards,
Nikhil

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User12789
Level 3
Level 3
10 sign-ins First solution authored 5 sign-ins

Here are the waveforms. The first shows the glitches and the missing complementary outputs. This application is a BLDC motor controller written from scratch and uses CCU8 slices to generate three complementary outputs (Uh, Ul, Vh, Vh, Wh, and Wl). The arrows point to the glitches and to places where output is completely missing.

The second photo shows correct output on all channels.

I only have XMC4400 and XMC4700 boards so I can't test this on other XMC devices.

motorglitch1.pngCorrectWaveforms.png

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ncbs
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50 likes received 250 sign-ins 250 replies posted

Hi @User12789,

Please find the project attached used to test the same. This project has been created for XMC4700 relax kit. The project has a single CCU8 slice unit, and out1 and out2 have been connected to two GPIOS (P5.10 and P0.1). The outputs were observed for a various range of frequencies from Hz to kHz range. 

The period register value is kept at 16000 and the compare register value was kept at 20000 (which is not period value + 1). No glitches were observed in either out1(st) or out2(inverted st1). 

Hence, the statement present in the reference manual holds true - "generating a 0% duty cycle signal is always possible by setting a value in the compare register bigger than the one programmed into the period register". 

Regards,
Nikhil

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User12789
Level 3
Level 3
10 sign-ins First solution authored 5 sign-ins

Did you try period value + 2? That's the case where I observed the glitches.

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ncbs
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Hi @User12789,

Yes, there were no glitches observed when compare value was set to period value + 2 too.

Regards,
Nikhil

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ncbs
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Hi @User12789,

Is it possible to share a minimal project so that we can recreate the issue at our end?

Regards,
Nikhil

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