Level 2
Hello Forum,
It is possible that I can uns a USIC Interface in this matter that the SPI Master is send
16 clocks, and read the 16 Bit from two slave into the Input Register of the XMC.
I don't care if the two individual data words were then nested in a 32-bit data word
Slave 1 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
Slave 2 b1 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
In-Buffer a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 a12 b12 a13 b13 a14 b14 a15 b15
Is such a mode of operation possible with an XMC USIC
Best regards
Ebbe Sand
It is possible that I can uns a USIC Interface in this matter that the SPI Master is send
16 clocks, and read the 16 Bit from two slave into the Input Register of the XMC.
I don't care if the two individual data words were then nested in a 32-bit data word
Slave 1 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
Slave 2 b1 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
In-Buffer a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 a12 b12 a13 b13 a14 b14 a15 b15
Is such a mode of operation possible with an XMC USIC
Best regards
Ebbe Sand
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