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User19319
Level 1
Level 1
Guys! Right now I am facing a very hard challenge. I have asked two questions here, apparently, no one responded to me.

The Questions I post here:

1. How to use UART debug trace in XMC4800 Automation V2 Board

2. My XMC4800 board with the Ethcat slave function always runs exceptionally

My main problem is the second one, and the UART debug issue is the debug solution I want to use. But the Automation Board V2 don't wire the related pins from XMC4800.

To overcome the main problem, I think my const arrays are too many, I decided to use the external SDRAM available in Automation Board.

I referenced the EBU SDRAM source code from : https://es.technikum-wien.at/bel/bel4_ezb_public/tree/090f7fd07fef20698f98602d5862417b92288b03/XMC_U...

Then I wrapped the initialization source code like below:


__WEAK void init_sdram_component()
{
/* EBU Clock is divided by 2 - To program the divider connecting a parent and its child clock node*/
XMC_SCU_CLOCK_SetEbuClockDivider(2U);

/* Enable EBU Clock */
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_EBU);

EBU_MUX_Init();
EBU_Init();
}


Then call this function in SystemInit from system_XMC4800.c, I put it into the end of the SystemInit like below:


__WEAK void SystemInit(void)
{
delay(10000000);
memcpy(g_chipid, CHIPID_LOC, 16);

SystemCoreSetup();
SystemCoreClockSetup();
init_sdram_component();
}


I also modified the linker_script.ld, the attachment is the link script, and I make a summary of my changes:


MEMORY
{
FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x00200000
FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x00200000
PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000
DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000
SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000
DSRAM_3_external(!RX) : ORIGIN = 0x60000000, LENGTH = 0x4000000
}


The bold line is my adding, then I added 3 new sections:


SDRAM_RODATA :
{
. = ALIGN(4); /* section size must be multiply of 4 */
__sdram_rodata_start = .;
*(SDRAM_RODATA)
. = ALIGN(4); /* section size must be multiply of 4 */
__sdram_rodata_end = .;
} > FLASH_1_cached AT > DSRAM_3_external

SDRAM_BSS :
{
. = ALIGN(4); /* section size must be multiply of 4 */
__sdram_bss_start = .;
*(SDRAM_BSS)
. = ALIGN(4); /* section size must be multiply of 4 */
__sdram_bss_end = .;
} > DSRAM_3_external AT > DSRAM_3_external

SDRAM_DATA :
{
. = ALIGN(4); /* section size must be multiply of 4 */
__sdram_data_start = .;
*(SDRAM_DATA)
. = ALIGN(4); /* section size must be multiply of 4 */
__sdram_data_end = .;
} > DSRAM_3_external AT > DSRAM_3_external


Finally, I put attribute statements before any global variables that I strongly suspect like below:


__attribute__((section("SDRAM_BSS")))
static Control_Block _earth_control_block;

/* PDOs and their contents: */
__attribute__((section("SDRAM_RODATA")))
static const ESS_PDO_ENTRY PDO1600Entries[] = {
{ 0x7040, 1, 1 },
{ 0x7040, 2, 1 },
{ 0x7040, 3, 1 },
{ 0x7040, 4, 1 },
{ 0x7040, 5, 1 },
{ 0x7040, 6, 1 },
{ 0x7040, 7, 1 },
{ 0x7040, 8, 1 },
{ 0x8000, 0, 8 }, //xsafety control byte
{ 0x8001, 0, 8 }, //A1 control byte
{ 0x8002, 0, 32 }, //A1 demanded current
{ 0x8011, 0, 8 }, //A2 control byte
{ 0x8012, 0, 32 }, //A2 demanded current
{ 0x8021, 0, 8 }, //A3 control byte
{ 0x8022, 0, 32 }, //A3 demanded current
{ 0x8031, 0, 8 }, //A4 control byte
{ 0x8032, 0, 32 }, //A4 demanded current
};


Unfortunately, the main problem is still existing, I am begging you guys to help me to analyze the root cause from my whole story?

Thanks!
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