Problem bind ERU ISR to Core 1, 2..5

[SmileOn1]

Hello! I can't bind an interrupt from ERU to any core other than 0. I set up the ERU_Interrupt_1_KIT_TC397_TFT example, changed the pins for my project and launched it successfully. After that, I changed the type of service (in the macro parameters IFX_INTERRUPT and IfxSrc_init) to 2 (which corresponds to Core 1):

IFX_INTERRUPT(SCUERU_Int0_Handler, 0, ISR_PRIORITY_SCUERU_INT0); -> IFX_INTERRUPT(SCUERU_Int0_Handler, 2, ISR_PRIORITY_SCUERU_INT0);

IfxSrc_init(g_ERUconfig.src, IfxSrc_Tos_cpu0, ISR_PRIORITY_SCUERU_INT0); ->  IfxSrc_init(g_ERUconfig.src, IfxSrc_Tos_cpu1, ISR_PRIORITY_SCUERU_INT0);

 In this form, my project does not work. Perhaps I did not take into account some specific architecture, does anyone know?

[SmileOn1 · Accepted solution]

Problem solved. In the IFX_INTERRUPT macro, the numbering of cores in a row (cpu1 - 1, cpu2 - 2). Whereas in the IfxSrc_Tos enumeration, the numbering is shifted for dma (value 1). I mistakenly specified an enumeration value in IFX_INTERRUPT.

[Owen_Su]

Hi,

    Thanks for  sharing this problem. And you can create a new thread if you have any other questions, Infineon will continue to provide you with better services.

BR,

Owen