Announcements

Help us improve the Power & Sensing Selection Guide. Share feedback

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Not applicable
Sorry,

this function don't get into the isr and I don't no why?

Thank you for any help!

Bernd

void CCU40_1_IRQHandler(){
P0_7_toggle();
}

in main:
//Disable the clock gating for CCU4 module
SCU_GENERAL->PASSWD = 0xC0U;
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_CCU40_Pos);
SCU_GENERAL->PASSWD = 0xC3UL;
//Enable the prescaler block
SET_BIT(CCU40->GIDLC, CCU4_GIDLC_SPRB_Pos);
//Set the prescaler value
WR_REG(CCU40_CC41->PSC, CCU4_CC4_PSC_PSIV_Msk, CCU4_CC4_PSC_PSIV_Pos, (uint32_t)7U); //
//Control of CCU4 timer slices
CCU40->GCTRL = (uint32_t)0;
//Set the period of the timer
WR_REG(CCU40_CC41->PRS, CCU4_CC4_PRS_PRS_Msk, CCU4_CC4_PRS_PRS_Pos, (uint32_t)1000U); //
//Enable the synchronized transfer of the period value into the active register
SET_BIT(CCU40->GCSS, CCU4_GCSS_S1SE_Pos); //
//Set which interrupt line the timer interrupt is directed toward
WR_REG(CCU40_CC41->SRS, CCU4_CC4_SRS_CMSR_Msk, CCU4_CC4_SRS_CMSR_Pos, (uint32_t)0x02); // 10BForward to CC4ySR2 //
//Enable interrupt generation on comparison match
SET_BIT(CCU40_CC41->INTE, CCU4_CC4_INTE_PME_Pos); //
//Enables the timer
SET_BIT(CCU40->GIDLC, CCU4_GIDLC_CS1I_Pos); //
//Start the timer
SET_BIT(CCU40_CC41->TCSET, CCU4_CC4_TCSET_TRBS_Pos); //

NVIC_SetPriority(CCU40_1_IRQn, 0xC0); //This CMSIS function configures node 1 to priority level 192 (lowes Priority)
NVIC_ClearPendingIRQ(CCU40_1_IRQn); //This function clears node 1 pending status
NVIC_EnableIRQ(CCU40_1_IRQn); //This function enables node 1 for interrupt request generation

P0_7_set_mode(OUTPUT_PP_GP);
0 Likes
1 Reply
Not applicable
I found the mistake:

WR_REG(CCU40_CC41->SRS, CCU4_CC4_SRS_POSR_Msk, CCU4_CC4_SRS_POSR_Pos, (uint32_t)0x01)// CCU40_1_IRQn = 22, !< CCU40 SR1 Interrupt

instead of:

WR_REG(CCU40_CC41->SRS, CCU4_CC4_SRS_CMSR_Msk, CCU4_CC4_SRS_CMSR_Pos, (uint32_t)0x02)
0 Likes