No Interrupt At USIC0_CH1

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Good afternoon I do need help!

I'm going to get an interrupt via Hyper Terminal to a XMC1200 but nothing happend.

THANK YOU FOR ANY HELP

Here my code:

#define RxD_ISR IRQ_Hdlr_9

#define FDR_STEP 472
#define BRG_PDIV 44
#define BRG_DCTQ 16
#define BRG_PCTQ 0



//-----------------------------------------------------------------------------------------------------------
void InitUartCh1(void){
//USIC Configuration Disable the USIC0 clock gating
SCU_GENERAL->PASSWD = 0x000000C0UL;
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_USIC0_Pos);
while ((SCU_CLK->CLKCR)&(SCU_CLK_CLKCR_VDDC2LOW_Msk)){;}
SCU_GENERAL->PASSWD = 0x000000C3UL;

//Disable UART mode before configuring all USIC registers to avoid unintended edges
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 0);
//Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel
//modes for the different device operating modes.
USIC0_CH1->KSCFG |= (1 << USIC_CH_KSCFG_MODEN_Pos) | (1<< USIC_CH_KSCFG_BPMODEN_Pos); //Kernel State Configuration Register
//Fractional Divider mode selected
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_DM_Msk, USIC_CH_FDR_DM_Pos, 2 );//ok
//Step Value
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_STEP_Msk, USIC_CH_FDR_STEP_Pos, FDR_STEP);
//PreDivider for CTQ, PCTQ = 0, Denominator for CTQ, DCTQ = 16
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PCTQ_Msk, USIC_CH_BRG_PCTQ_Pos, BRG_PCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_DCTQ_Msk, USIC_CH_BRG_DCTQ_Pos, BRG_DCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PDIV_Msk, USIC_CH_BRG_PDIV_Pos, BRG_PDIV);
//Configuration of USIC Shift Control
//Transmit/Receive LSB first is selected, Transmission Mode (TRM) = 1, Passive Data Level (PDL) = 1
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_PDL_Msk, USIC_CH_SCTR_PDL_Pos, 1);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_TRM_Msk, USIC_CH_SCTR_TRM_Pos, 1);
//Set Word Length (WLE) & FRame Length (FLE)
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, 7);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_WLE_Msk, USIC_CH_SCTR_WLE_Pos, 7);
//Configuration of USIC Transmit Control/Status Register
//TBUF Data Enable (TDEN) = 1, TBUF Data Single Shot Node (TDSSM) = 1
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDEN_Msk, USIC_CH_TCSR_TDEN_Pos, 1);
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDSSM_Msk, USIC_CH_TCSR_TDSSM_Pos, 1);
//Configuration of Protocol Control Register
//Sample Mode (SMD) = 1, Stop Bit is selected, Sample Point (SP) = 2, Pulse Length (PL) = 0
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SMD_Msk, USIC_CH_PCR_ASCMode_SMD_Pos, 1);
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_STPB_Msk, USIC_CH_PCR_ASCMode_STPB_Pos, 0); //2 Stopbits
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SP_Msk, USIC_CH_PCR_ASCMode_SP_Pos, 6);
//TBIF is set to simplify polling
WR_REG(USIC0_CH1->PSR_ASCMode, USIC_CH_PSR_RIF_Msk, USIC_CH_PSR_RIF_Pos, 1);

//Standard receive buffer interrupt event is enabled.
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos, 1);
//Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x01000000); //DPTR = 0, SIZE = 1

// Standard Receive Buffer Interrupt Node Pointer - Output SR3 activated (STBINP = 3)
USIC0_CH1->RBCTR |= (0x00UL << USIC_CH_RBCTR_SRBINP_Pos); //SR0
//Configuration of Channel Control Register
//Parity generation is disabled
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 2);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_PM_Msk, USIC_CH_CCR_PM_Pos, 0);
//Data Pointer & Buffer Size for Transmitter Buffer Control - DPTR = 64, Size = 6
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos, 0x06000040);

P0_6_set_mode(INPUT);
USIC0_CH1->DX0CR |= (0x02UL << USIC_CH_DX0CR_DSEL_Pos);

NVIC_SetPriority(USIC0_0_IRQn, 0xC0);
NVIC_ClearPendingIRQ(USIC0_0_IRQn);
NVIC_EnableIRQ(USIC0_0_IRQn);

}//End InitUartCh1
//-----------------------------------------------------------------------------------------------------------
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3 Replies
DRubeša
Employee
Employee
First solution authored First like received
HI,

I cannot offer you exact answer to your question while it would be easier for me that you tell me what do you want to achieve, but I can offer you suggestion/advice. Try to do first DAVE CE project that works. Meaning open an empty DAVE CE project, add UART APP and configure it with the parameters you need (baudrate, data bits, stop bits, and so on). Then run that project on your board and verify that it is working. If you have issues even then take a look at UART_XMC_Lib_XMC12 example. So why I´m suggesting this? Because once you have example that is doing exactly that you expect, you can then do step by step debugging and see which instructions are performed on direct register access level. This way you can easily which line in your upper code is maybe wrong/missing/or redundant.

Let me know if you need additional help but then give me some more details in advance (baudrate, data bits, parity, stop bits, pin that are you using, etc.).

Best regards,
Deni
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Not applicable
good offer.. is it for every one? 🙂
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Not applicable
Hi Deni,

Sorry, I'm not a friend of "App's" because I always will be the master of my own code and I'm going to try to understand the controller right.
I could solve some problems in the case you prefer but I think it would be better to develop a better documentation of the controler!

Here is the solution of my problem:
I've forgotten only this line

/Configuration of Transmitter Buffer Control Register, configuration of Receiver Buffer Control Register
USIC0_CH1->RBCTR |= (((0 << USIC_CH_RBCTR_LIMIT_Pos)& USIC_CH_RBCTR_LIMIT_Msk)|((1 << USIC_CH_RBCTR_LOF_Pos)& USIC_CH_RBCTR_LOF_Msk));

Thank you and regards,
Bernd
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