Is this a documentation error in Board_Users_Manual_XMC4500_Relax_Kit-V1_R1.1_rel ...

[#1]

Hi
Apologies if this not the right place to go about this, but in Board_Users_Manual_XMC4500_Relax_Kit-V1_R1.1_released.pdf, Figure 6 I2S section shows I2C-Slave1 SD (Data) as being on pin P5.0 but the master (3) is on P0.5, ditto WA on P0.6 (but master on U1C0, slave on U2C0.
I looked at the xmc4500_rm_v1 2_2012_12_.pdf section 17.12, table 17-23, and it seems that the IIS slave and master should be on the same pins as grouped for SPI-Slave2 & SPI-Master4. That is, Master & Slave WA = P0.6, Master & Slave SD = P0.5.

Can someone confirm this?

[#2]

Hi SharmanJ,

From what I see on the board manual, it should be the documentation error.
Both I2C-Master3 and I2C-Slave1 should be using the same channel which is USIC1 Channel 0 (U1C0).
It is not possible to used SCK on U1C0 and SC & WA on U2C0.
Moreover, U2C0.DX2A is not P0.6 but P5.3.
Therefore, I believe it should be like what you said, the Slave1 SD pin should be P0.5 (U1C0.DX0B).

Thank you for your feedback.
I will submit this for the documentation update.