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User6412
Level 4
Level 4
I have realized the IIC communication without FIFO, so I write all my data in USIC1_CH1->TBUF[0] - everything work. But as soon as I add the Transfer FIFO - nothing more work.
So I just replaced USIC1_CH1->TBUF[0] by USIC1_CH1->IN[0] register.
The FIFO is configured as follow:


USIC1_CH1->TBCTR = (16UL << USIC_CH_TBCTR_DPTR_Pos & USIC_CH_TBCTR_DPTR_Msk) |
// Data Pointer
// This bit field defines the start value for the transmit
// buffer pointers when assigning the FIFO entries to
// the transmit FIFO buffer. A read always delivers 0.
// When writing DPTR while SIZE = 0, both transmitter
// pointers TDIPTR and RTDOPTR in register
// TRBPTR are updated with the written value and the
// buffer is considered as empty. A write access to
// DPTR while SIZE > 0 is ignored and does not modify
// the pointers.
(3UL << USIC_CH_TBCTR_SIZE_Pos & USIC_CH_TBCTR_SIZE_Msk);
// Buffer Size
// This bit field defines the number of FIFO entries
// assigned to the transmit FIFO buffer.
// 000B The FIFO mechanism is disabled. The buffer
// does not accept any request for data.
// 001B The FIFO buffer contains 2 entries.
// 010B The FIFO buffer contains 4 entries.
// 011B The FIFO buffer contains 8 entries.
// 100B The FIFO buffer contains 16 entries.
// 101B The FIFO buffer contains 32 entries.
// 110B The FIFO buffer contains 64 entries.
// 111B Reserved

USIC1_CH1->RBCTR = (24UL << USIC_CH_RBCTR_DPTR_Pos & USIC_CH_RBCTR_DPTR_Msk) |
// Data Pointer
// This bit field defines the start value for the receive
// buffer pointers when assigning the FIFO entries to
// the receive FIFO buffer. A read always delivers 0.
// When writing DPTR while SIZE = 0, both receiver
// pointers RDIPTR and RDOPTR in register TRBPTR
// are updated with the written value and the buffer is
// considered as empty. A write access to DPTR while
// SIZE > 0 is ignored and does not modify the
// pointers.
(3UL << USIC_CH_RBCTR_SIZE_Pos & USIC_CH_RBCTR_SIZE_Msk);
// Buffer Size
// This bit field defines the number of FIFO entries
// assigned to the receive FIFO buffer.
// 000B The FIFO mechanism is disabled. The buffer
// does not accept any request for data.
// 001B The FIFO buffer contains 2 entries.
// 010B The FIFO buffer contains 4 entries.
// 011B The FIFO buffer contains 8 entries.
// 100B The FIFO buffer contains 16 entries.
// 101B The FIFO buffer contains 32 entries.
// 110B The FIFO buffer contains 64 entries.
// 111B Reserved
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User6412
Level 4
Level 4
I found the reason. If I write direct in to the TBUF[0] register - the protocol errors will be ignored (USIC_CH_PSR_IICMode_ERR_Msk and USIC_CH_PSR_IICMode_NACK_Msk). But if I use the FIFO (register IN[0]) - transmission will stop at the first error. I don't know why it is so differently). This code check errors and restarts the protocol:


/**
* Any errors?
*/
if(USIC1_CH1->PSR_IICMode & (USIC_CH_PSR_IICMode_ERR_Msk | USIC_CH_PSR_IICMode_NACK_Msk)) {
// Clear error bits
USIC1_CH1->PSCR |= 0x3FF;
// Flush transmit FIFO buffer
USIC1_CH1->TRBSCR |= USIC_CH_TRBSCR_FLUSHTB_Msk;
// Modify Transmit Data Valid
WR_REG(USIC1_CH1->FMR, USIC_CH_FMR_MTDV_Msk, USIC_CH_FMR_MTDV_Pos, 2);
i2c_power.state = 0;
}
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