IIC slave address and FIFO

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Assuming IIC 10bit master transmit mode and FIFO mode, when the slave receives the slave address bytes, it can generate FIFO receive buffer event interrupt on slave?
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so I´ve used the I2C_SLAVE_EXAMPLE_XMC4500 that is built around DAVE APPs and while this example is slightly different than conditions that you mention, the answer is the same: you will NOT generate an receive buffer event interrupt by receiving address bytes. Take a look at the following figure:


This is the exact moment when address bytes are received (you can see at the bottom address 0xA (10) that was sent from the Master device). As you can see, three flags are raised:SLSEL (Slave Select), SRC (Start Condition Received), and RSIF (Receiver Start Indication Flag). If you would need to enter interrupt routine once the address is received, I suggest to use SRC as a trigger (yes, I´m aware that receiving SRC does not mean that address is correct but you may check also for the bit PSR.SLSEL which should be set if the address are matching). You need to enable PCR.SCRIEN bit and provide protocol interrupt routine.

Best regards,