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User8819
Level 4
Level 4
Hello,

I am using my own code, no apps, no library to run I2C as master and I am encountering problem when attempting to read from slave. Both RX and TX FIFOS are configured for 16 elements. When transmitting I would expect that I can load to FIFO "without" any checks 16 elements. (Maybe 17 if first one goes directly to transmitter).
This seems to be not true. At start of each sequence FIFOs are flushed. Then I load correct sequence of bytes for read operation with correct TDF codes. When I load 8 bytes, all 8 are transmitted, I receive what I expect, no problem. When I load 9 bytes, 9 bytes are transmitted ending with stop bit, but very often immediately after stop appears one additional byte on output. Slave does not expect it and therefore I get NAK. It appears like in TX FIFO was one byte more. If I transmit 10bytes, again sometimes I get on output 11.
If before filling FIFO I insert
while((USIC1_CH0->TRBSR & USIC_CH_TRBSR_TFULL_Msk)){};
problem disappears.

Tried also to increase both FIFOs to 32 elements, behavior is same. CH1 of USIC1 is not using FIFO. Start pointers are configured correctly.

Has anyone seen the same problem?

rum
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4 Replies
jferreira
Employee
Employee
10 sign-ins 5 sign-ins First like received
Hi,

Can you share your FIFO setup and code showing the error?
You may also have a look to the implementation of the I2C_MASTER APP or the I2C CMSIS driver.
We usually check if the FIFO is full while filling it:

            /* Write to FIFO till Fifo is full */
while((XMC_USIC_CH_TXFIFO_IsFull(i2c->i2c) == false))
{
if(i2c->info->xfer.tx_num - i2c->info->xfer.tx_cnt == 1)
{
XMC_I2C_CH_MasterReceiveNack(i2c->i2c);
}
else
{
XMC_I2C_CH_MasterReceiveAck(i2c->i2c);
}
i2c->info->xfer.tx_cnt++;

if(i2c->info->xfer.tx_num - i2c->info->xfer.tx_cnt == 0)
{
break;
}
}



Regards,
Jesus
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User8819
Level 4
Level 4
Hello Jesus,

1. I also check for fifo full, but this is not a problem because fifo is 16 and I want to transmit only 10 elements including stop. Before tx sequence I clear fifo.

2. Also XMC_I2C example fails, I tried it, but it fails in different mode. When configured in polling mode it hangs in Tx, there is while when it waits until all bytes are transmitted. App runs for a while then it stops there.

/*make sure data is transmitted from FIFO*/
while (!XMC_USIC_CH_TXFIFO_IsEmpty(handle->channel)){}

There is one byte remaining in fifo, data is valid for transmission, transmission enabled, it does not transmit it. All other flags seems correct.

2. Also when configured in interrupt mode, it hags by not setting tx_completion_0=1, simply interrupt stops. One byte remains in fifo.


another insight if it may help for my code. The last byte that is coming out at he end of my sequence (after stop bit) without that I write it to fifo is usually repeated 3rd byte of "device address" or first or second "received" byte.

Received byte appears on output, then slave responds of course with NAK.

setting up I2C is pretty simple so there is no need to post the code and it is not possible to isolate it form rest of code.

maybe some silicon bug?

rum
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User8819
Level 4
Level 4
Hello,

What could be reason that data is not transmitted on I2C, it is in TX FIFO but not going out? FIFO filling level shows some number, TCSR status, TVD=1, TDSSM=1, TDEN=1, TDVTR=0. TRBSR.TEMPTY=0. Sometimes xmc hangs in this situation.

rum
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User15015
Level 1
Level 1
Welcome! First reply posted
Did you solve the problem?
I think I have the same problem
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