How SP0 and SP1 bits work in the SHSCFG register? (XMC1100, VADC module)

[#1]

Hi,

I found these two bits in the datasheet of the XMC1100: SP0 and SP1. I found them in the chapter VADC module, SHS0 registers. They are take place in the SHSCFG register. I wrote a program, which uses five input channels. I set continuous conversion.
The datasheet says about these two bits:

Sample Pending on Group x
0: No sample pending
1: Group x has finished the sample phase

I debug the program. These two bits did not change, these were always 0.

How are these bits work? Could somebody tell me?

Rjani

[Travis]

Hi,

There is no need for you to touch this SP0 and SP1. May I know what do you want for your VADC configuration as I might have an example for u?

[#3]

Hi Travis,

I am new in ARM Cortex M0 architecture. So I would like to learn as much as I can about it. I just test the VADC module and I see how it works.
So I asked about SP0 and SP1. I did not see the working of these bits.

Could you tell me, when will these bits set to 1 or 0?

Rjani