FLASH PARTITION

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

what the  FLASH_0_cached and  FLASH_0_uncached, FLASH_1_cached and  FLASH_1_uncached are used for in P2G XMC4700? Can you tail me the purpose of this flash partition? The MEMORY is like this:

MEMORY
{
FLASH_0_cached(RX) : ORIGIN = 0x08010000, LENGTH = 0x0008000
FLASH_0_uncached(RX) : ORIGIN = 0x0C010000, LENGTH = 0x00008000
FLASH_1_cached(RX) : ORIGIN = 0x080C0000, LENGTH = 0x001E0000
FLASH_1_uncached(RX) : ORIGIN = 0x0C0C0000, LENGTH = 0x001E0000
PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000
DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000
SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000
}

I see the FLASH_0 region is only used for 

.reset :
{
KEEP(*(.reset));
. = ALIGN(256);
} > FLASH_0_cached AT > FLASH_0_uncached = 0xFF

When I modify the memory into just 1 flash region:

MEMORY
{
FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x001E0000
FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x001E0000
PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000
DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000
SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000
}

.reset :
{
KEEP(*(.reset));
. = ALIGN(256);
} > FLASH_1_cached AT > FLASH_1_uncached = 0xFF

It doesn't work. I suffer with this issue for weeks, please anyone help me.

0 Likes
1 Solution
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su , I think I found it!

When I switch abm firmware from p2g model code into a new xmc4700 196x2048 project, everything else is the same, and it's work! It took me 2 weeks to solve this issue, can't believe it. Thank you for your support. Hope to receive more support from you if I have another problem.

Sincerely.

View solution in original post

0 Likes
28 Replies
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    The XMC4000 series flash memory has a feature. One space has two address ranges. The power consumption is higher when there is a cache, but the performance is much higher. Because there is no waiting when reading Flash, just like when executing from RAM, the power consumption is low when there is no cache. You need to configure the waiting period according to the bus speed, otherwise a bus error will occur.

Owen_Su_0-1665380042267.png

    In this part, Flash_0 is used for reset and Flash_1 is used for other storage, you can also change the address of Flash_1 and then use Flash_1 for reset, as long as the ORIGIN address of Flash_1 is within this range. Hope this can help you.

Owen_Su_2-1665380389814.png

Owen_Su_1-1665380128592.png

Regards,

Owen_Su

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

@Owen_Su hi,

When I use just one FLASH1 section, my project doesn't work. I don't know why. Here is ld file and error in disasembly.

90670_2-1665385878289.png90670_3-1665385888321.png

 

 

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    There may be other instructions calling Flash_0 in the code, so there is a mismatch. It is recommended that you compare the corresponding address changes with and without Flash_0. If these questions are related to software updates, I suggest you take a look at the ASCLoader file I gave you and try again. Hope this can help you.

Regards,

Owen_Su

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Thanks for your reply. I will take a look at ASC boot mode but now I'm currently trying to get the job done with ABM_0 boot mode. I see that I could upload the application firmware into the flash region I want, just like in example code. But when bootloader code run into system reset, MCU doesn't run application code as I expected. 

void BL_FlashABM0_Restart(void)
{
/* Restart in alternative bootmode 0 */
/* Clear the reset cause field for proper reset detection of the ssw */
XMC_SCU_RESET_ClearDeviceResetReason();
/* Set ABM0 as boot mode in SWCON field of STCON register */
XMC_SCU_SetBootMode(XMC_SCU_BOOTMODE_ABM0);
/* Trigger power on reset */
PPB->AIRCR = 1 << PPB_AIRCR_SYSRESETREQ_Pos |0x5FA<<PPB_AIRCR_VECTKEY_Pos | 0x1 << PPB_AIRCR_PRIGROUP_Pos;
}

The reset function and header 

static const ABM_Header_t __attribute__((section(".flash_abm"), used))
ABM0_Header = {
.MagicKey = ABM_HEADER_MAGIC_KEY,
.StartAddress = 0x08010000, /* Start Flash Physical Sector 1 */
.Length = 0xFFFFFFFF,
.ApplicationCRC32 = 0xFFFFFFFF,
.HeaderCRC32 = 0xE176A4E6
};

is just the same as in the example and I still not figured out why it doesn't work. Linker script MEMORY and flash_abm SECTION are ok just like the example too. Can you give me some advice for this situation?

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

90670_0-1665480996812.png

Hi @Owen_Su ,

I just find out that when bootloader run into upload new application code into ABM_0 region, I see there is data in there (address 0x08010000), but after trigger system reset to enter to ABM_0 mode, data from address 0x08010000 is gone. I think this is why my code doesn't work. Can you explain for me why this happend?

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    I tested the example "XMC4700 / 4800 USB Mass Storage Device Bootloader and In Application Programming" with my Kit_XMC47_relax, it works well, so you can try again from the following points:

    1) You can compare the codes of P2G and Kit_XMC47, they are different in the allocation and definition of Flash, so you need to modify the address of Flash_0 and Flash_1, and you need to set the start address to the corresponding position.

Owen_Su_0-1665544376384.png

    2) Use the code example "XMC4700 / 4800 USB Mass Storage Device Bootloader and In Application Programming" to test on your board. 

    3) Confirm the size of the firmware you want to update, and ensure that the address allocation is sufficient without overlapping.

    4) The output file format has already changed to 'Binary', so you need to check whether your format meet the requirements ;

    5) Follow the steps in the document to set the image_ 20Hz is the firmware before the update, and your own is the updated firmware to confirm whether the address assignment is correct. You can also exchange the following positions to confirm whether your code is correct.

    Hope this can help you.

Regards,

Owen_Su

 

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su ,

I think I have done all of it just like the example for my P2G kit. One think I still not sure is the AMB_0 header ApplicationCRC32 and length. In the example it's set both two to 0xFFFFFFFF. Document said it's because when application code is scattered. How I know when the code is scattered or not? Below is my blynk LED application code linker_script file. Can you take a look for me, I don't know if something is wrong with this. I tested so many times. It works in normal boot mode (ORIGIN 0x08000000 and 0x0C000000). When I build bin file for ABM_0, I just change ORIGIN into 0x08010000, 0x0C010000

================LINKER_SCRIPT=================================

/**
* @file XMC4700x2048.ld
* @date 2020-11-18
*
* @cond
*********************************************************************************************************************
* Linker file for the GNU C Compiler v1.3
* Supported devices: XMC4700-E196x2048
* XMC4700-F144x2048
* XMC4700-F100x2048
*
* Copyright (c) 2015-2020, Infineon Technologies AG
* All rights reserved.
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer,
* must be included in all copies of the Software, in whole or in part, and
* all derivative works of the Software, unless such copies or derivative
* works are solely in the form of machine-executable object code generated by
* a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* at XMCSupport@infineon.com.
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-09-03:
* - Initial version
*
* 2016-03-08:
* - Fix size of BSS and DATA sections to be multiple of 4
* - Add assertion to check that region SRAM_combined does not overflowed no_init section
*
* 2017-04-07:
* - Added new symbols __text_size and eText
*
* 2017-04-20:
* - Change vtable location to flash area to save ram
*
* 2020-11-18:
* - ensure that .reset section size is a multiple of the page size
*
* @endcond
*
*/

OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)

stack_size = DEFINED(stack_size) ? stack_size : 2048;
no_init_size = 64;

MEMORY
{
/* FLASH_0_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x00008000
FLASH_0_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x00008000 */
FLASH_1_cached(RX) : ORIGIN = 0x08010000, LENGTH = 0x001F0000
FLASH_1_uncached(RX) : ORIGIN = 0x0C010000, LENGTH = 0x001F0000
PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000
DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000
SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000
}

SECTIONS
{
/* TEXT section */

/* .reset :
{
KEEP(*(.reset));
. = ALIGN(256);
} > FLASH_1_cached AT > FLASH_1_uncached = 0xFF */

.text :
{
KEEP(*(.reset));
sText = .;
*(.text .text.* .gnu.linkonce.t.*);

/* C++ Support */
KEEP(*(.init))
KEEP(*(.fini))

/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)

/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)

*(.rodata .rodata.*)
*(.gnu.linkonce.r*)

*(vtable)
. = ALIGN(4);
} > FLASH_1_cached AT > FLASH_1_uncached

.eh_frame_hdr : ALIGN (4)
{
KEEP (*(.eh_frame_hdr))
} > FLASH_1_cached AT > FLASH_1_uncached

.eh_frame : ALIGN (4)
{
KEEP (*(.eh_frame))
} > FLASH_1_cached AT > FLASH_1_uncached

/* Exception handling, exidx needs a dedicated section */
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH_1_cached AT > FLASH_1_uncached

. = ALIGN(4);
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH_1_cached AT > FLASH_1_uncached
__exidx_end = .;
. = ALIGN(4);

/* DSRAM layout (Lowest to highest)*/
Stack (NOLOAD) :
{
__stack_start = .;
. = . + stack_size;
__stack_end = .;
__initial_sp = .;
} > SRAM_combined

/* functions with __attribute__((section(".ram_code"))) */
.ram_code :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__ram_code_start = .;
*(.ram_code)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__ram_code_end = .;
} > SRAM_combined AT > FLASH_1_uncached
__ram_code_load = LOADADDR (.ram_code);
__ram_code_size = __ram_code_end - __ram_code_start;

/* Standard DATA and user defined DATA/BSS/CONST sections */
.data :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__data_start = .;
* (.data);
* (.data*);
*(*.data);
*(.gnu.linkonce.d*)

. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);

. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);

. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__data_end = .;
} > SRAM_combined AT > FLASH_1_uncached
__data_load = LOADADDR (.data);
__data_size = __data_end - __data_start;

__text_size = (__exidx_end - sText) + __data_size + __ram_code_size;
eText = sText + __text_size;

/* BSS section */
.bss (NOLOAD) :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__bss_start = .;
* (.bss);
* (.bss*);
* (COMMON);
*(.gnu.linkonce.b*)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__bss_end = .;
} > SRAM_combined
__bss_size = __bss_end - __bss_start;

/* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */
__shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end);

USB_RAM (__bss_end + __shift_loc) (NOLOAD) :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
USB_RAM_start = .;
*(USB_RAM)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
USB_RAM_end = .;
} > SRAM_combined
USB_RAM_size = USB_RAM_end - USB_RAM_start;

ETH_RAM (USB_RAM_end) (NOLOAD) :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
ETH_RAM_start = .;
*(ETH_RAM)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
ETH_RAM_end = .;
. = ALIGN(8);
Heap_Bank1_Start = .;
} > SRAM_combined
ETH_RAM_size = ETH_RAM_end - ETH_RAM_start;

/* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/
.no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) :
{
Heap_Bank1_End = .;
* (.no_init);
} > SRAM_combined

/* Heap - Bank1*/
Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start;

ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")

/DISCARD/ :
{
*(.comment)
}

.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }

/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }

/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }

/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }

/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }

/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }

/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }

/* Build attributes */
.build_attributes 0 : { *(.ARM.attributes) }
}

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Owen_Su_0-1665562989726.png

    The default address of Flash in P2G board is shown in the figure above, you can modify it according to the figure. And here is the link:Infineon-P2G_Software_User_Manual .

    Maybe the address you modified will conflict with other functions. And here is one thing that ABM-0/ABM-1 cannot be entered with power on reset, and P2G kit doesn't have a button1, so if you want to trigger ABM, you need to change the condition to enter into the interrupt. And P2G have many differences with Kit_xmc47, so  it cannot copy the folder or the codes directly, after checking the points above, if this doesn't work, you can share your project with us. Hope this can help you.

Regards,

Owen_Su

 

 

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su ,

Thanks for your response, I will take a look.

"P2G have many differences with Kit_xmc47, so  it cannot copy the folder or the codes directly", can you explain more precise for me this point?

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Owen_Su_1-1665624836049.png

Owen_Su_2-1665625210248.png

  Just like the figure above, some address will be not within the region, and generally, we do not easily modify the functions and allocations in linker scripts.

 

 

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su,

I think the problem when I use this example with my P2G board is because the ABM_0 firmware of the example is loaded into flash address 0x08010000, which is preserved in P2G board. I think if I can change the load address  of USB upload firmware from 0x08010000 to 0x08020000 to appropriate with P2G (also change linker scripte and ABM_0 header accordingly), it will work I guess.

But I don't know how to change the destination address of upload firmware through USB. Can you guide me this part?

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Owen_Su_0-1665647913904.png

    You can refer to this part, but I'm not sure whether it can work or not.

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    Maybe you can try our XMC Flasher, which can be use to reprogram the firmware applications of P2G. I think that D2G/P2G/S2G can use this tool to do the update, and other products like: kit_xmc can use SDcard firmware update and Bootloader. Hope this can help you.

Owen_Su_0-1665731910440.png

Regards,

Owen_Su

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su ,

But XMC Flasher cannot program 2 regions of application code, which is what I want. I want to build a bootloader with memory in flash contains 3 regions: bootloader, ABM_0 and ABM_1. Which is possible in XMC_4700 kit right?

P2G cannot do this because it has different flash region than other XMC4700 MCU? I though the bootloader and other relative bootmode is depend on XMC4700 MCU, not the dev kit itself. So I still don't know why P2G, which has XMC4700 just like relax kit, but cannot use bootloader. Or because XMC4700 on P2G is different hardware from regular XMC4700?

0 Likes
lock attach
Attachments are accessible only for community members.
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su ,

Because I'm very rush now so I need to ask you another question, hope to hear your answer as soon as possible. I'm testing my firmware with P2G kit, I modify linkerscript so my firmware ORIGIN is 0x08000000 and 0x0C000000. LENGTH = 0x00010000. So firmware stored in flash cannot be located in other regions than 0x08000000 - 0x080100000 (same for 0x0CXXXXXX) right? But when I look at the disassembly  code, there are some codes in the region starting from 0x08020000. Why is that happening? I thought firmware must be located from ORIGIN and have length like I configed in linker script? Thank you.

 

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    As your description, your firmware is stored in the right place for sure,  and you can find the reason why 0x08020000 has some codes in "main.c". This part has already used for ABM header.

Owen_Su_0-1665977960448.png

 

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su ,

ABM header is located at 0x0800FFE0, I check memory view, it was there, so ABM header cannot be located at 0x08020000 am I right? Not just 0x08020000, other regions like 0x08040000 also has codes. I still don't know why those regions have codes. Please explain to me this part, also could you answer my other above question about P2G?

90670_0-1665979930847.png

 

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    The "MEMORY" part in linker script only defines the BOOTLOADER executable part, and other codes will be placed in the application executable part, which ABM Header defines the start address, and the length is 0xFFFFFFFF. So when you power-on reset or debug, there will place the application codes somewhere in "APPLICATION executable".

    For the reason why you can't build a bootloader with your P2G, we need some time to verify whether it is caused by the difference between software and hardware, I will feedback to you as soon as there is a result, thanks for your understanding.

Regards,

Owen_Su

Owen_Su_0-1665988937076.png

 

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    Can you share your project with us, so we can test it on our board. In addition, when you followed the example "USBD_MS_BOOTLOADER_IAP", have you mapped USB Mass Storage correctly? At which step did you have problems? Thanks for your understanding.

Regards,

Owen_Su

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su , I think I found it!

When I switch abm firmware from p2g model code into a new xmc4700 196x2048 project, everything else is the same, and it's work! It took me 2 weeks to solve this issue, can't believe it. Thank you for your support. Hope to receive more support from you if I have another problem.

Sincerely.

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

hi @Owen_Su , 

can you give me the linkerscript file of bootloader USBD_MS_BOOTLOADER_IAP for ABM_1 mode? because the region for ABM1 header is out range of my bootloader firmware, so I want to know how to set up flash region for ABM1.

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi, @90670 ,

    You can refer to the "Reference manual" of XMC4700 to find out the address of ABM-1, and you can refer to the thread here:  https://community.infineon.com/t5/XMC/ABM-Header/td-p/301478, which included an example to setup the ABM_1 mode. Hope this can help you.

Owen_Su_0-1666056296159.png

Regards,

Owen_Su

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su , thread link you gave me cannot access.

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

Hi @Owen_Su , is the size of abm0 firmware limited in 64kb from 0x0C010000 to 0x0C01FFFF in sector 1 of flash and the size of abm1 firmware limited in 64kb from 0x0C020000 to 0x0C02FFFF in sector 2 of flash?

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Yes, you can refer to this figure:

Owen_Su_2-1666069979230.png

 

 

 

0 Likes
90670
Level 4
Level 4
25 replies posted 25 sign-ins 10 questions asked

This figure just tell me the beginning of flash region of ABM, not the limit of it. I want to know if there is madantory maximum size of ABM.

0 Likes
Owen_Su
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 50 likes received

Hi,

    Our relevant documents do not specify the mandatory ABM flash size, but you can check the address distribution of XMC400 series Flash, the former 8 sectors are 16kB,  the following sectors are 128KB and 256KB. For the applications with program update requirements, the former 64KB can be used for Bootloader, the latter 64KB used for  Analog EEPROM, the bigger sector will place the user program.

Owen_Su_0-1666072533094.png

Regards,

Owen_Su

0 Likes