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Hi,
I'm using Encoder posif app in Dave 4.4.2, for XMC4800. Since I want a 32-bit counter, I check the checkbox called "Revolution counter". Unfortunately, at startup the higher part of the word, namely the 16-bit revolution counter, starts immediately to count. When I move the encoder inputs so that the lower part changes from zero to a different value, the revolution counter stops counting and behaves correctly. It seems that 0 value on 16-bits lower counter to be equivalent to "enable free run" in the 16-bits higher (revolution) counter.
Does anybody use this App?
Regards
Solved! Go to Solution.
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Hi @User20456 ,
I see that the behavior followed by the 32-bit counter is already explained in one of your older threads here : Solved: XMC4800 - 32 bit counter down direction - Infineon Developer Community
Here, the counting scheme is done by the hardware and cannot be changed. The CCU4yCMC.TCE bitfield enables concatenation of slices and configuration for HW is done automatically internally with an edge-aligned mode timer.
So this means the timer slice containing the LSBs should always have the TCE bitfield set to 0 and the MSB slice will have the TCE bit field set to 1. Section 23.2.9 Timer Concatenation in XMC4700 XMC4800 Reference Manual describes about the CCU4yCMC.TCE bitfield.
Hope this answer your query or else feel free to add or create a newer thread for any other issue.
Best Regards,
Aashita
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Hi @User20456 ,
Can you please try elaborating this to us " When I move the encoder inputs so that the lower part changes from zero to a different value, the revolution counter stops counting and behaves correctly." ? This will help us understand the issue clearly.
Best Regards.
Aashita
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Hi,
when lower 16-bits counter = 0, then higher 16bits counter increments as if it was free-running. This is a wrong behaviour.
when lower 16-bits counter != 0, then higher 16 bits counter increments only on the overflow of the lower 16 bits counter. This is a correct behaviour.
I attach my original file encoder_posif_conf.c (encoder posif Dave driver) and the patch that seems to resolve the bug. What do you think about?
Regards
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Hi @User20456 ,
I see that the behavior followed by the 32-bit counter is already explained in one of your older threads here : Solved: XMC4800 - 32 bit counter down direction - Infineon Developer Community
Here, the counting scheme is done by the hardware and cannot be changed. The CCU4yCMC.TCE bitfield enables concatenation of slices and configuration for HW is done automatically internally with an edge-aligned mode timer.
So this means the timer slice containing the LSBs should always have the TCE bitfield set to 0 and the MSB slice will have the TCE bit field set to 1. Section 23.2.9 Timer Concatenation in XMC4700 XMC4800 Reference Manual describes about the CCU4yCMC.TCE bitfield.
Hope this answer your query or else feel free to add or create a newer thread for any other issue.
Best Regards,
Aashita