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jonatanzeidler
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The XMCLib EtherCAT abstraction requires the XMC_ECAT_PORT_CTRL_t config struct, which asks for MDIO (SMI) related configs like phyaddr_offset and mdio (XMC_ETH_MAC_PORT_CTRL_MDIO_t). I understand that this is needed to allow me to configure the PHYs via the MDIO using XMC_ECAT_ReadPhy() and XMC_ECAT_WritePhy() and that the configured phyaddr_offset is added transparently to the phy_addr I provide to these functions.

My main question is: Does the EtherCAT cuircuit access the MDIO at any time without me calling those functions? And if so, what does it need MDIO access for?

The Reference Manual, Section 16.3.2.2 PHY Address Configuration, states that ideally the PHY addresses should be consecutive and match 0 for port 0 and 1 for port 1, considering the phyaddr_offset. What is the rational behind this? And why "ideally"? Do I have a problem if the logical PHY addresses are not matching 0 and 1 on my board?

I suspect, it uses MDIO to check the link status in case one does not provide a dedicated link signal. In case that correct, could you confirm that the EtherCAT cuircuit doesn't need the MDIO for anything else?

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sujatapatil
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Hi Jonathan,

Link monitoring can be done by ,

1> Dedicated link signal 

2> Get phy  link register status using MDIO read.

ECAT core  uses dedicated link signal which is connected to PHY transceiver's LED signal  . This helps in faster detection of Link which is required for ESC. MDIO access is slow compared  to dedicated signal detection.

Though we can read link status register using MDIO read , there is no way to inform ECAT stack . So dedicated link is required .

Thanks

Sujata

 

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sujatapatil
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Hi , 

Here MDIO bus is used  for configuration of PHY transceiver  and for link monitoring . APIs XMC_ECAT_ReadPhy() and XMC_ECAT_WritePhy() are used for this operation .  

The communication between ethernet controller and phy transceiver is using serial interface known as MDIO . To communicate with PHY  , it needs address . For phy transceiver address is configured  during hardware design. So  if phy has  4  phy_id pins ,  you can pull up/down to decide address and configure address from 00 to 0F during hardware design.

Please refer  reference design for this pin . You can plan any other address in range of 0-15  by hardware configuration and the same address you need to configure in software which is currently 0 and 1 in reference code.

Thanks

Sujata

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jonatanzeidler
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If I understand you correctly, you use XMC_ECAT_ReadPhy() and XMC_ECAT_WritePhy(), where you can provide a PHY address and therefore consecutive PHY addresses are not required. But do you know the answer to my question? Namely whether the EtherCAT hardware in the XMC utilizes the MDIO automatically? And thus, is it important to have the logical addresses 0 and 1 as stated to be "ideal" in the reference manual?

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sujatapatil
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Hi 

The phy transreceiver used in xmc4800 has had 5 phy_id pins , out of which phy 1 to phy 4 are multiplexed with RXD0- RXD3 which is connected to XMC port pin and configured for RX purpose . xmc_eschw.c has configuration for this.

So now you are left with only one address pin which is phy_id0  . So you have constraint to use address 0 and 1 for port 0 and port 1 respectively.

please refer board user manual and refer  schematic "Figure 14 XMC EtherCAT Phy Board Schematic: Input and Output Phy (see Revision 1.3)"

Hope this will help you

Thanks

Sujata

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I am not talking about any evaluation kit.  And I am well aware about how to use bootstrapping to configure a PHY address. My question is about the EtherCAT cuircuit included in the XMC4800 Mikrocontroller. Please only reply if you have input regarding my question.

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sujatapatil
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10 likes received 100 sign-ins 25 solutions authored

Hi 

The phy transreceiver used in xmc4800 has had 5 phy_id pins , out of which phy 1 to phy 4 are multiplexed with RXD0- RXD3 which is connected to XMC port pin and configured for RX purpose . xmc_eschw.c has configuration for this.

So now you are left with only one address pin which is phy_id0  . So you have constraint to use address 0 and 1 for port 0 and port 1 respectively.

please refer board user manual and refer  schematic "Figure 14 XMC EtherCAT Phy Board Schematic: Input and Output Phy (see Revision 1.3)"

Hope this will help you

Thanks

Sujata

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jonatanzeidler
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If others wonder about this, too, sujatapatil responded on a ticked and confirmed my suspicion above, that the EtherCAT hardware only accesses the MDIO bus for checking a link when there is no dedicated LINK signal. In other words: you only need consecutive PHY addresses if you don't have a dedicated LINK signal.

Thanks!

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sujatapatil
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10 likes received 100 sign-ins 25 solutions authored

Hi Jonathan,

Link monitoring can be done by ,

1> Dedicated link signal 

2> Get phy  link register status using MDIO read.

ECAT core  uses dedicated link signal which is connected to PHY transceiver's LED signal  . This helps in faster detection of Link which is required for ESC. MDIO access is slow compared  to dedicated signal detection.

Though we can read link status register using MDIO read , there is no way to inform ECAT stack . So dedicated link is required .

Thanks

Sujata

 

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