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Dear community members,
I have a question according to "OSC_ULP Oscillator Watchdog (ULPWDG)" in chapter 11.6.9.1 in Reference Manual V3.6 of XMC4500 family.
I see that "In case of external crystal failure the clock source switches automatically to the Internal
Slow Clock Source generating f_OSI.".
I just want to ask you whether there is a possibility to check if the internal slow clock source is in use instead of the external crystal. I assumed the SCU.HDCR.RCS bit changes automatically on failure of external crystal but it does not. Is there maybe any bit I can read out for that purpose?
Thanks!
Best regards,
autoUser
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Hi @autoUser,
Could you let us know the source of your external clock supply? Can you let us know the tolerance value of the same?
Regards,
Nikhil
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Hi @ncbs,
we use a 32.768 kHz external clock with a input voltage range from 1.6 to 3.6 V. The tolerance is +-25 ppm.
Regards,
autoUser
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Hi @ncbs,
I didn't hear anything over the last weeks. Do you have any new information for me please?
Thanks.
Regards,
autoUser