Cannot run two independent SPI_MASTER module concurrently

[#1]

I have two sensors with SPI interface that I am trying to run at the same time. They are on different USIC modules (USIC0.0 and USIC2.0). When I start SPI transactions at the same time on both masters, I get lots of SPI_MASTER_STATUS_BUSY returns. Why is that? Are they sharing control structures or interrupts?

EDIT:

Note that my code is structured like this:

void S1Receive() {
  handle_s1_data();
  run_s1();
}

void S2Receive() {
  handle_s2_data();
  run_s2();
}

void main() {
  init();
  run_s1();
  run_s2();
}

So in every SPI interrupt, another SPI transaction is started.

When I run only one of the SPIs like this, I never get a busy error.

[chismo]

Hello,

As the two USIC channels are from different module instances, they are completely independent from one another.
However, there is only one CPU to service both USIC channels.

Are the 2 interrupts of the same priority? If not, could it be that one event is triggering all the time at higher priority such that the 2nd event is never serviced?

Regards,
Min Wei

[#3]

No, they have the same priority. Like I said, what I'm wondering about is why I receive SPI_MASTER_STATUS_BUSY from SPI_MASTER_Receive / SPI_MASTER_Transfer function. (One of the sensors is a TLI4970 with single-wire SPI so I use SPI_MASTER_Receive for it).

Depending on which one I start first, the one started later will complete one spi transaction and then return SPI_MASTER_STATUS_BUSY when I want to run it again.

EDIT: So.... this does not happen when I configure the transmit interrupts to have the same preemption priority as the receive interrupts. So the problem is presumably that the transmit interrupts are getting starved by the receive interrupts. Now of course DAVE says "In order to avoid receive FIFO data overwriting, it is recommended to configure higher preemption priority for the receive interrupt." - could you maybe explain what that means exactly? Will I be fine if I make sure the receive FIFO is larger than my SPI transactions? Why is this a problem anyway, after all receive and transmit always happen in lockstep...

[chismo]

Hello,

I think the statement is referring to the case of a single USIC channel.
Here, it makes sense that receive interrupt has the higher priority such that any old received data is cleared from the buffer before new data is received (due to the next transmit sequence).

For your case, since they are different USIC modules, I don't think this statement applies.

Regards,
Min Wei