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Level 4
Level 4

I see from different examples that CCU4 is able to perform capture of (one slice timer) based on CC4yST state which is a result of compare operation (of other slice timer). Is it possible to do capture based on "period match"?
If yes, please provide some configuration example. I was wondering if setting compare value to period value or 0 would do the job? Which one is better? There is no clear explanation in manual how ST status is generated if compare value is equal period value or 0.

In CCU4 application note is written:

As long as the timer register value is equal or greater than the compare register value, the Status Bit
(CCST or even named CCU4xSTy) will be set to one (=1). Otherwise it is set to zero (=0).

So, understanding this means, that if compare value=period value and timer reaches compare value status bit is set 1 and one clock later timer overflows and status bit should be set 0. So there should be a ST pulse equal 1 clock.

But figure 15 in application note shows duty cycle 0 !!!! So how is it?

Another question: period match interrupt is generated when timer first time reaches period value or one clock later?


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May I know what is it that you want to achieve?

Do you want to generate a PWM waveform or perform a period/duty cycle captured?