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User8683
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Level 4
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I am trying to get configuration step 3 of section 2.7 working with a source queue but I am not sure what is required beyond what I have done

"3) Configure the request source to be gated by this level signal (CCU4x.ST) and be triggered by the service request generated by CCU4x period match (check interconnect section in reference manual). This is selected in control registers of each request source."

a) I have enabled ARBCNT counting to drive the slice 3 timer and can see the timer increments and is wrapping at the required period level
b) on timer slice 3 register INTE, I enable interrupt on period match PME bits
c) on timer slice 3 register SRS, I set the POSR bits to 2 to send the service request to service request line 2
d) I can see that the INTS CMUS bit and PMUS bit are being set
e) on adc QCTRL0 register, I set the TMWC, TMEN bits, I leave the GTSEL as 0 to gate on ST3 and leave XTSEL as 0 to trigger on service request line 2, I set the XTMODE to 1 for a downward edge

I can see the QCTRL0 GTLVL bit value is changing, the QCTRL0 XTLVL does not seem to change and I don't seem to be getting any changes to the ADC ARBCFG BUSY bit.

If other registers are involved in linking the TIMER to the ADC in this manner, I would appreciate the details. Otherwise if anyone can tell me what I have not done, that would be appreciated.

Thanks,

Jason
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