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User8683
Level 4
Level 4
I am attempting to perform the calibration steps outlined in errata ADC_AI.004 based on my interpretation of the wording, but when I add it to the code, my subsequent PWM triggered ADC sampling following the calibration no longer executes. In particular, the call to write BRSMR.LDEV prevents subsequent calls to the ADC result event handler. I am not otherwise using LDEV in my code.


/**
* Perform calibration to compensate for bug ADC_AI.004
*/
SET_BIT( pVADCGlobal->GLOBCFG, VADC_GLOBCFG_SUCAL_Pos);
while (RD_REG( pSHS->SHSCFG, SHS_SHSCFG_STATE_Msk, SHS_SHSCFG_STATE_Pos ) != 0)
{
*(uint32_t *)0x480340E0 = 0x00008000;
*(uint32_t *)0x480340E4 = 0x00008000;
}
for (i=0; i<1; i++)
{
for (j=0; j<9; j++)
{
pVADCGlobal->BRSSEL[0] = 0x01;
SET_BIT( pVADCGlobal->BRSMR, VADC_BRSMR_LDEV_Pos );
while (RD_REG( pVADCGlobal->GLOBEFLAG, VADC_GLOBEFLAG_REVGLB_Msk, VADC_GLOBEFLAG_REVGLB_Pos ) != 1);
ADCResult = pVADCGlobal->GLOBRES;
}
*(uint32_t *)0x480340E0 = 0x00008000;
*(uint32_t *)0x480340E4 = 0x00008000;
}



At this stage in the code, I have not yet enabled the result event or the IRQ.

I think that the errata needs to be updated with more details and should include some source code along with any cleanup code that is required.
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11 Replies
Not applicable
Hi Jason,

We have release an example project for the calibration workaround.
The current Errata text might not be details enough as the whole calibration workaround.
We are preparing a new Errata text for the complete calibration sequence.

Please go to DAVE Example portal:
http://www.infineon.com/cms/en/product/promopages/aim-mc/dave_downloads.html
and search for 'ADC_AI.004' and you will see the calibration code example.
In the example, we have set the ADC to internal reference but you may want to comment out that particular line if you are using external reference.
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User8683
Level 4
Level 4
Thanks for that. I got something working and it appears to be applicable.

It would be good to have an XMC1100 version of this project too since the ADC system is different than for the XMC1200 and XMC1300.
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Not applicable
Hi Jason,

Yes, we are currently preparing for it now.
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Not applicable
Hi Jackson,

i took a look at the calibration sequence oft he Example-project (ADC_Cal_BG_Source_Example_XMC13).

I found out some uncertainties in the example-code.

1. Line 202 in the ADC_SU_Calibration-function:

	// Enable SU calibration ADC
VADC->GLOBCFG = (1 << VADC_GLOBCFG_SUCAL_Pos & VADC_GLOBCFG_SUCAL_Msk)|
(1 << VADC_GLOBCFG_DPCAL0_Pos & VADC_GLOBCFG_DPCAL0_Msk)|
(1 << VADC_GLOBCFG_DIVWC_Pos & VADC_GLOBCFG_DIVWC_Msk)|//write control
(0 << VADC_GLOBCFG_DIVA_Pos & VADC_GLOBCFG_DIVA_Msk)|//fadci=8MHz
(0 << VADC_GLOBCFG_DPCAL1_Pos & VADC_GLOBCFG_DPCAL1_Msk);



Why the automatic post-calibration is disabled in group 0 (DPCAL0) and enabled in Groupt 1? The post-calibration in group 0 won’t be enabled in the further code!!!! So no post-calibration is added for group 0, only for group 1!

The comment says the fadci is 8Mhz. But a Write with 0 to the DIVA-Mask results in fadci = fADC/2 = 16Mhz.


2. Line 234 in the ADC_PG_Calibration-function:

VADC->GLOBCFG |= (0 << VADC_GLOBCFG_DPCAL1_Pos & VADC_GLOBCFG_DPCAL1_Msk);


If DPCAL1-Bit is already 1, this Line has no effect, because of the OR! The right code to enable the DPCAL-Bit is:

VADC->GLOBCFG &= ~ (VADC_GLOBCFG_DPCAL1_Msk);


3. Line 236 in the ADC_PG_Calibration-function:
*SHS0_CALOC0 = 0x80000000;//only SHS1 needs to reset the offset calibration

Why only the SHS1 needs to reset the offset calibration values???


4. Line 260 in the ADC_PG_Calibration-function
if(adc_result_aux == 0);

What should this line of code do?

5. Line 286 in the IRQ-Handler
*SHS0_CALOC1 = 0x8000; //offset calibration clear as per errata ADC_AI.004 AA_Step

Why only clear the offset calibration values of Group 1? There are also some channels in group 0 in the example.

I'm a little bit confused, so it would be nice if you can help me!

PS: Sorry for my bad english 🙂
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Not applicable
Hi Olli_K ,

For point 1:
Calibration is only required to be done on one group and it will be calibrated for both group.
Hence, only group1 need to be enabled.
As for the DIVA value, the comment is wrong. We will update it.

For point 2:
Yes, you are correct. Basically it is use to ensure the post calibration on group1 is enabled.
Using AND is the appropriate way. We will update it.

For point 3:
Sorry, the comment is wrong. That code of line is to disabled the calibration in SHS0.

For point 4:
This is a redundant code to prevent warning in DAVE3. When a variable is set and not use, DAVE3 will give warning.

For point 5:
Refers to answer for point 1.
Since we only enable group 1, we only need to clear CALOC1.

Sorry for causing confusion.
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Not applicable
Hi Jackson,

thanks for your very quick response. This helps me a lot to understand the calibration sequence. Thank you!
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Not applicable
Hi Jackson,

I have one more question about the calibration mechanism of the ADC:

When will the post calibration cycles be executed?

1. The reference manual says that calibration cycles can be executed before or after a conversion sequence (v1.1 16.5.3 Calibration).
For example I understood that the background request source sequence is such a conversion sequence. All channels of the
background request source will be scanned and after that, the post calibration cycles are executed.
So i have to clear offset calibration values after each background request source sequence.

2. The errata sheet says that postcalibration cycles are executed automatically after each conversion (v1.4 ADC_AI.004 ADC Calibration Weakness).
So i have to clear offset calibration values after each result value.

What is right?
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Not applicable
Hi,

The post calibration is done after all requested conversions have been completed.
If there is only one request and none other pending, the post calibration will be done after that conversion.
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User8720
Level 1
Level 1
Is this bug still inside the MCU or has it been fixed over the year?
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Travis
Employee
Employee
First like received
Hi,

This issue had been fixed for the new AB steps.
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chismo
Employee
Employee
First like received
Hello,

The bug has been fixed in the AB-step of the device.
This is reflected in the latest AB-step errata sheet v1.3 12-Jun-2015, which can be found in the link below:
http://www.infineon.com/cms/en/product/channel.html?channel=db3a30433c1a8752013c1aa35a6a0029#ispnTab...

Regards,
Min Wei
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