Hello,

I opened an old program to update my electronic card by reinstalling WICED Studio 6.6.1.

When attempting to program my card with JTAG , I received the following error message:

"Making snip.scan-BCM943362WCD4.bin
Downloading Bootloader ...
"**** OpenOCD failed - ensure you have installed the driver from the drivers directory, and that the debugger is not running **** In Linux this may be due to USB access permissions. In a virtual machine it may be due to USB passthrough settings. Check in the task list that another OpenOCD process is not running. Check that you have the correct target and JTAG device plugged in. ****"
Downloading DCT ...
"**** OpenOCD failed - ensure you have installed the driver from the drivers directory, and that the debugger is not running **** In Linux this may be due to USB access permissions. In a virtual machine it may be due to USB passthrough settings. Check in the task list that another OpenOCD process is not running. Check that you have the correct target and JTAG device plugged in. ****"
Downloading Application ...
"**** OpenOCD failed - ensure you have installed the driver from the drivers directory, and that the debugger is not running **** In Linux this may be due to USB access permissions. In a virtual machine it may be due to USB passthrough settings. Check in the task list that another OpenOCD process is not running. Check that you have the correct target and JTAG device plugged in. ****"
Resetting target"

Could someone please explain the steps to install or test the setup correctly?

We have been using WICED SDK for our FW application running on STM32 sensor hardware.
We use WICED to connect to WiFi AP.

Application uses HTTPS to connect to a Cloud application.

I did not see any reference of HTTPs proxy client in the SDK. 
Is it supported in the SDK ?

Greetings,

We're having an issue connecting to SOME of our prototype hardware via Seger JLINK  SWD mode.  It works fine on some boards but not others.  While I cannot yet rule out some manufacturing defect - if there is one its not revealed in a 3d x-ray of the PCBA.

Our problem is described in this thread [CYW43907] MCU JTAG Connect Fail but the answer is not very helpful other than we may be looking in the wrong direction.

To be clear, we're using a Murata 1GC module.

Build options are: JTAG=jlink-native JLINK_PATH="/usr/bin/" JLINK_EXE="JLinkExe" JLINK_INTERFACE=SWD download download_apps

Build machine is linux based - but replicated on a Windows 10 platform (with appropriate changes in above for windows machines.

Error text is:

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

Cannot connect to target.

I've tried using JLinkExe from the command line, on a working target:

sean_fendt@ssf:~/src/tf0001$ JLinkExe -device CYW43907 -if SWD -speed 4000
SEGGER J-Link Commander V6.52e (Compiled Oct 16 2019 12:19:21)
DLL version V6.52e, compiled Oct 16 2019 12:19:11

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled May 17 2019 09:50:41
Hardware version: V9.30
S/N: 59304943
License(s): GDB
VTref=3.354V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Device "CYW43907" selected.


Connecting to target via SWD
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Data endian: little
Main ID register: 0x411FC144
I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
TCM Type register: 0x00010001
MPU Type register: 0x00000800
System control register:
  Instruction endian: little
  Level-1 instruction cache disabled
  Level-1 data cache disabled
  MPU enabled
  Branch prediction enabled
Memory zones:
  [0]: Default (Default access mode)
  [1]: APB-AP (AP0) (DMA like acc. in AP0 addr. space)
Cortex-R4 identified.
J-Link>q

And on a non-working target:

sean_fendt@ssf:~/src/tf0001$ JLinkExe -device CYW43907 -if SWD -speed 4000
SEGGER J-Link Commander V6.52e (Compiled Oct 16 2019 12:19:21)
DLL version V6.52e, compiled Oct 16 2019 12:19:11

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled May 17 2019 09:50:41
Hardware version: V9.30
S/N: 59304943
License(s): GDB
VTref=3.353V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Device "CYW43907" selected.


Connecting to target via SWD
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

Cannot connect to target.
J-Link>q

I have the feeling something is on the edge of working, but so far I don't know what.  Extensive experiments with strapping, reset timing, etc has not been revealing.  Any thoughts on things to check would be helpful.

when I read the register of CHIPCOMMON_SR_CONTROL1 to check if the firmware initialized sr engine, it failed, so I wondered how to enable or disable the sr feature, or the firmware initialize the sr feature itself?

Infineon AIROC Wi-Fi/Bluetooth Combo STM32 Expansion Pack is an extension of the CMSIS-Pack standard established by Arm. The pack is compliant with the full CMSIS-Pack standard, with additional requirements/restrictions on the final pack to meet the STM standard.

This SW pack uses libraries from the Infineon ModusToolbox environment. 

• Infineon GitHub landing space - https://github.com/Infineon/stm32-connectivity/releases
• Infineon AIROC Wi-Fi/BT STM32 Expansion Pack v1.4.0 – https://github.com/Infineon/stm32-connectivity/releases/download/release-v1.4.0/Infineon.Connectivit...
• Infineon AIROC Connectivity STM32 User Guide v1.4.0 – https://github.com/Infineon/stm32-connectivity/blob/release-v1.4.0/Documentation/STM32ConnectivityEx...

What's Included?

• Infineon AIROC Wi-Fi / Bluetooth Combo Release for STM32H7xx, H5xx, U5xx & L5xx MCUs family

What Changed?

v1.4.0

• Added STM32H5xx support
• PAL improvements and fixes
• New Examples added for STM32H747I-DISCO and STM32U575I-EV
• Wi-Fi offload - TCP/IP Keepalive offload

Supported STM32 Boards and MCU

• STM32H747I-DISCO Discovery kit and STM32H7xx
• NUCLEO-H563ZI board and STM32H5xx
• STM32U575I-EV Evaluation board and STM32U5xx
• STM32L562E-DK kit and STM32L5xx

Supported Connectivity Modules

Infineon's CYW43xxx Wi-Fi-BT combo chip family:

• CYW43012
• CYW43439 / CYW43438 / CYW4343W
• CYW4373 / CYW4373/E

Example apps inside the Pack

Wi-Fi Scan Example

This example initializes the Wi-Fi device and starts a Wi-Fi scan without any filter and prints the
results on the serial terminal.

Refer to Projects/STM32H747I-DISCO/Applications/wifi_scan/readme.txt for more details

Wi-Fi Onboarding with Bluetooth LE Example

This example demonstrates a simultaneous usage of Wi-Fi and BLE functionality of CYW43xxx combo
devices. It uses BLE on the combo device to help connect the Wi-Fi to the AP.

Refer to Projects/STM32H747I-DISCO/Applications/ble_wifi_onboarding/readme.txt for more details

Azure RTOS NetXDuo Wi-Fi UDP echo server

This application provides an example of Azure RTOS/NetXDuo stack usage. It shows how to develop a
NetX UDP server to communicate with a remote client using the NetX UDP socket API.

BLE Hello Sensor Example

This code example demonstrates the implementation of a simple Bluetooth Stack functionality in GAP
Peripheral role. During initialization the app registers with LE stack to receive various notifications
including bonding complete, connection status change and peer write.

Refer to Section BLE Hello Sensor Example in STM32 connectivity expansion pack user guide for more details.

Wi-Fi TCP keepalive offload

The TCP keepalive offload feature of the Low Power Assistant (LPA) improves the power consumption
of your connected system by reducing the time the Host needs to stay awake to support a TCP keepalive
request. This example describes how to enable TCP keepalive offload and configure four different
sockets for TCP keepalive that can be incorporated into your project from LPA Middleware.

Refer to Projects/STM32H747I-DISCO/Applications/wifi_tko/readme.txt for more details.

Compatible Software

Future release - v1.5.0

• Add Infineon Wi-Fi 6/6E combo chip (CYW55573 - 2x2 Wi-Fi 6/6E, CYW55513 - 1x1 Wi-Fi 6/6E) support.
• TCPKA keepalive (payload) offload with multiple sessions.
• Wake-on-WLAN - wowlpf support for remote wake-up.
• TLS over TKO
• MQTT keepalive

More information

• README.md
• STM32 Connectivity Expansion Pack User Guide
• Cypress Semiconductor, an Infineon Technologies Company
• Infineon GitHub
• ModusToolbox

Hello.

I have the sequent problem:

I have developed a board with CYW943907 and an FPGA.

I have to store FPGA configuration file (1.5Mbyte of size) in the external FLASH (8MByte of size).

I read WICED-Resource-Filesystem.pdf and I understand that I can put the FPGA configuration file in resources/apps/<MY_APP>/fpgaConfig.bin.

I can read fpgaConfig.bin with resource_get_readonly_buffer and I'm happy.

But my problem is that in the future it might be possibile to update this file but I cannot find any resource_write_readonly_buffer API to do this operation.

I'm not sure but I understand that OTA can only update APP and not resource.

Can some one help me ?

Good afternoon. I am facing HTTPS speed issue on CYW943907AEVAL1F platform.
When downloading a file via HTTPS, the speed drops almost 8 times, relative to HTTP (without encryption).
Interestingly, the chip has a crypto core.
Perhaps someone has already worked on this issue?
I'm attaching the test results.