Wi-Fi Combo Forum Discussions

Hello everyone,

I need to work on a legacy product that requires WICED SDK 2.4.1 which requires Java JRE 1.6.0, the thing is that our company does not allow us to install Java so I was looking to use Corretto, but even with Corretto 8 or 21 the install of WICED IDE fails.

The question is, how does WICED IDE installer identifies JAVA as installed in the computer?

BTW, I had to use an old installer since I have not seen any installer published on this site.

Hello,

I opened an old program to update my electronic card by reinstalling WICED Studio 6.6.1.

When attempting to program my card with JTAG , I received the following error message:

"Making snip.scan-BCM943362WCD4.bin
Downloading Bootloader ...
"**** OpenOCD failed - ensure you have installed the driver from the drivers directory, and that the debugger is not running **** In Linux this may be due to USB access permissions. In a virtual machine it may be due to USB passthrough settings. Check in the task list that another OpenOCD process is not running. Check that you have the correct target and JTAG device plugged in. ****"
Downloading DCT ...
"**** OpenOCD failed - ensure you have installed the driver from the drivers directory, and that the debugger is not running **** In Linux this may be due to USB access permissions. In a virtual machine it may be due to USB passthrough settings. Check in the task list that another OpenOCD process is not running. Check that you have the correct target and JTAG device plugged in. ****"
Downloading Application ...
"**** OpenOCD failed - ensure you have installed the driver from the drivers directory, and that the debugger is not running **** In Linux this may be due to USB access permissions. In a virtual machine it may be due to USB passthrough settings. Check in the task list that another OpenOCD process is not running. Check that you have the correct target and JTAG device plugged in. ****"
Resetting target"

Could someone please explain the steps to install or test the setup correctly?

Greetings,

We're having an issue connecting to SOME of our prototype hardware via Seger JLINK  SWD mode.  It works fine on some boards but not others.  While I cannot yet rule out some manufacturing defect - if there is one its not revealed in a 3d x-ray of the PCBA.

Our problem is described in this thread [CYW43907] MCU JTAG Connect Fail but the answer is not very helpful other than we may be looking in the wrong direction.

To be clear, we're using a Murata 1GC module.

Build options are: JTAG=jlink-native JLINK_PATH="/usr/bin/" JLINK_EXE="JLinkExe" JLINK_INTERFACE=SWD download download_apps

Build machine is linux based - but replicated on a Windows 10 platform (with appropriate changes in above for windows machines.

Error text is:

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

Cannot connect to target.

I've tried using JLinkExe from the command line, on a working target:

sean_fendt@ssf:~/src/tf0001$ JLinkExe -device CYW43907 -if SWD -speed 4000
SEGGER J-Link Commander V6.52e (Compiled Oct 16 2019 12:19:21)
DLL version V6.52e, compiled Oct 16 2019 12:19:11

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled May 17 2019 09:50:41
Hardware version: V9.30
S/N: 59304943
License(s): GDB
VTref=3.354V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Device "CYW43907" selected.


Connecting to target via SWD
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Data endian: little
Main ID register: 0x411FC144
I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
TCM Type register: 0x00010001
MPU Type register: 0x00000800
System control register:
  Instruction endian: little
  Level-1 instruction cache disabled
  Level-1 data cache disabled
  MPU enabled
  Branch prediction enabled
Memory zones:
  [0]: Default (Default access mode)
  [1]: APB-AP (AP0) (DMA like acc. in AP0 addr. space)
Cortex-R4 identified.
J-Link>q

And on a non-working target:

sean_fendt@ssf:~/src/tf0001$ JLinkExe -device CYW43907 -if SWD -speed 4000
SEGGER J-Link Commander V6.52e (Compiled Oct 16 2019 12:19:21)
DLL version V6.52e, compiled Oct 16 2019 12:19:11

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled May 17 2019 09:50:41
Hardware version: V9.30
S/N: 59304943
License(s): GDB
VTref=3.353V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Device "CYW43907" selected.


Connecting to target via SWD
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Found SW-DP with ID 0x5BA02477
CoreSight AP[0]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

Cannot connect to target.
J-Link>q

I have the feeling something is on the edge of working, but so far I don't know what.  Extensive experiments with strapping, reset timing, etc has not been revealing.  Any thoughts on things to check would be helpful.