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Good afternoon, WICED community!
I have a question about the CYW43907 chip and GSIO SPI master interface.
I want to stream the data from SPI slave and send it in a form of UDP packages to Wi-Fi.
I am using WICED Studio 6.4 to read the data from the SPI slave as fast as possible. However, I have noticed that the GSIO driver works in polling mode that increases CPU usage. Moreover, I can see the inter-byte delays and the delays caused by manually toggled CS line.
They equal about 0.8 microseconds for both inter-byte and chip select delay. Please, receive the waveform with the 5 MHz clock signal and CS signal captured by the oscilloscope.
The code I am using to send the SPI packets is the following:
wiced_result_t spi_send(uint8_t *tx_buf_ptr, uint8_t *rx_buf_ptr, int size, wiced_spi_device_t *spi_device_ptr)
{
platform_result_t result = PLATFORM_SUCCESS;
platform_spi_config_t config;
/* Chip select is not a GPIO when NULL. */
config.chip_select = ( spi_device_ptr->chip_select != WICED_GPIO_NONE ) ? &platform_gpio_pins[spi_device_ptr->chip_select] : NULL;
config.speed = spi_device_ptr->speed;
config.mode = spi_device_ptr->mode;
config.bits = spi_device_ptr->bits;
/* Activate chip select */
platform_spi_chip_select_toggle(&platform_spi_peripherals[spi_device_ptr->port], &config, WICED_TRUE );
/* SPI transfer after init and CS */
platform_spi_transfer_nosetup( &platform_spi_peripherals[spi_device_ptr->port], &config, tx_buf_ptr, rx_buf_ptr, size);
/* Deassert chip select */
platform_spi_chip_select_toggle(&platform_spi_peripherals[spi_device_ptr->port], &config, WICED_FALSE );
return (wiced_result_t) result;
}
It is a modified version of wiced_spi_transfer function that eliminates multiple SPI initialization (with the original function the delay between the packages is too big)
Given the results above, I have the following questions:
1. Is it possible to use SPI GSIO Master in interrupt or DMA mode?
The polling mode seems to be slow.
2. How can I decrease inter-byte distance and chip select delay in polling mode?
3. What is the maximum SPI GSIO Master clock frequency and corresponding data transfer rate tested by Cypress engineers?
4. Is it possible to increase the slew rate of SPI GPIO pins to increase the signal quality?
5. Does the next generation CYW54907 WiFI MCU has the same SPI GSIO functionality and bugs or did Cypress engineers improved the module?
Thank you in advance.
Best,
Sergei
Solved! Go to Solution.
- Labels:
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GPIO
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SPI
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Wireless MCU
- Tags:
- spi_gsio_master
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Hi Sergei
Thanks for all the effort you took in providing me with the plots
From the plots, I can understand the inter-byte delay is caused by the polling mechanism.
We cannot do much here to avoid the delay as this is hardware specific thing.
The driver code is as follows:
1. gsio_regs[spi->port].interface->data = data; --> The data is being fetch to the GSIO register
2. gsio_regs[spi->port].interface->ctrl |= GSIO_SB_BUSY; --> The GSIO start busy bit will be set (this will cause some delay - I suspect that 414 nano second)
3. gsio_wait_for_xfer_to_complete( spi->port ); --> GSIO will wait for transfer to complete i.e. polling will take place and hence the maximum inter-byte delay takes place
The above is a driver code which is been written as per the hardware algorithm and hence I said we cannot do much about it.
I hope this solves your doubt related to inter-byte delay.
Regarding the slew rate: I need to ask the internal team and will get back to you on this once I have a proper explanation about it.
Thanks and regards