I have an application, where I need to receive the data from FPGA and stream it through the WiFi link. Ideally, I want to utilize the whole bandwidth of the WiFi connection that is about ~150 Mbps for CYW43907 (theoretical) and ~450 Mbps for CYW54907 (theoretical).
My first question is the following:
1. What interface is the best to push the data from FPGA to Cypress WiFi MCUs?
I can see a few options for doing this:
I tried to work with SPI. However, I can't push the frequency of the SPI clock higher than ~ 13 MHz. It means that I can achieve a maximum of about 13 Mbps.
The datasheet says that Ethernet can have a maximum speed of 100 Mbps.
2. Can you confirm that I can achieve 100 Mbps connection speed of Ethernet by using the WICED SDK?
If not, what is the maximum?
Regarding the SDIO 3.0, I found that it can work in the following mode:
"SDR50: SDR up to 100 MHz (1.8 V signaling)."
According to "SD Specifications Part 1 Physical Layer Simplified Specification Version 3.01 May 18, 2010" this mode achieves only 50 Mbps.
3. Am I right that I can get a maximum of 50 Mbps by using the SDIO module on CYW43907/CYW54907?
Another promising option is USB 2.0 working in HS mode (480 Mbps according to Cypress datasheet )
4. Did you make speed test with USB 2.0 working in HS mode?
What it is the maximum speed of USB connection I can get by using WICED SDK?