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Hi all,
First of all: I am such a novise that I'm almost afaid of posting in this forum. Please have patience with me My experience with assembly code is next to nothing.
I would like to get started making a simple HID SUB devise. Just to find out how thing works, it could be a box with a button that is starting a routine in Windows when pressed.
So my questions are:
1. What USB controller is the easiest to start with?
2. What demo-board should I use?
3. What software should I use for writing code to the USB controller?
4. Is there any good reading material over the subject that you may refer to?
I'm sure there will be a 100 more questions, and I'm open to all input, advise and suggestions you might have!
CPUCS = bmCLKSPD1; // 48MHz
SYNCDELAY();
IFCONFIG = 0xA3; // drive IFCLK with internal 30MHz clock, use synchronous FIFOs.
SYNCDELAY();
REVCTL = 0x03;
SYNCDELAY();
EP2CFG = 0xA2;
SYNCDELAY();
FIFORESET = 0x80;
SYNCDELAY();
FIFORESET = 0x82;
SYNCDELAY();
FIFORESET = 0x00;
SYNCDELAY();
OUTPKTEND = 0x82;
SYNCDELAY();
OUTPKTEND = 0x82;
SYNCDELAY();
EP2FIFOCFG = 0x10;
SYNCDELAY();
The FPGA drives FIFOADR0 and FIFOADR1 low, and asserts SLRD and SLOE always (i.e it's always ready to accept data when data is available). I then tried a number of scenarios:
1) FPGA counts IFCLK rising edges for which FLAGC says "not empty". If the host sends 1024 bytes, the FPGA shows a count of 1024. So far so good.
2) FPGA calculates a 16-bit checksum of incoming data, using the same timing as in (1). If the host sends 1024 bytes, the FPGA shows a checksum consistent with it receiving 1024 bytes, comprising:
256 copies of byte 0
256 copies of byte 1
256 copies of byte 512
256 copies of byte 513
3) FPGA counts transitions (i.e where the current byte differs from the last), using the same timing as in (1). If the host sends 1024 bytes, all zero except buf[0]=1, buf[1] = buf[512] = 2, buf[513] = 3, the FPGA displays 0x3FF.
So it looks like for each 512 byte chunk, the FX2LP chip is sending the correct number of bytes to the FPGA, but it is just sending byte 0 alternating with byte 1, and throwing away everything else. It's as if the 9-bit offset which the slave FIFO uses to read from the endpoint buffer is being masked with 0x0001 somehow so rather than incrementing properly it just goes 0,1,0,1,0,1,0,1. The result is that irrespective of the number of 512-byte chunks sent, the checksum from (2) above comes out as 256 times the sum of the first pair of bytes in each chunk.
So my question is, am I merely doing something silly (missing register initialisations?) or have I damaged my FX2LP in some way?
I tried the exact same experiments with EP6, with exactly the same results. The other functions of the FX2LP which I have tested (e.g custom EP0 commands, EEPROM & RAM loads) appear to be working fine.
Any help gratefully received!
- Chris
Edit: PS I can correctly read back USB bulk transfers to the FX2LP, so I suspect it's something wrong with my slave FIFO config. Show Less
I am working on a new design which will use the CY7C68013A together with a FPGA to convert a USB Audio signal into SPDIF signal.
Details:
1. The CY7C68013A will act as the USB controller and convert the USB Audio signal into parallel data.
2. The FPGA will then covert the parallel data into SPDIF format.
3. Both (USB input and SPDIF output) of the above needs to support 24bit/192kHz audio data.
A few questions:
1. Is there any sample code for the CY7C68013A to act as an USB audio device and accept 24bit/192kHz audio data?
2. Can the CY7C68013A be programmed to act as a native USB Audio 2.0 device? Hence no custom USB driver is needed, user can use the generic USB audio driver comes with Windows.
Many thanks,
DM Show Less
A couple of questions --
1. On programming EP4FIFOPFH/PFL with DECIS = 1, PKTSTAT = 0 and IN: PKTS[1:0] = 0, PFC[5:0] = 32, after the external master writes the 32nd byte, the full flag gets asserted ( after a delay tXFLG). The external master continues to write an arbitrary number of bytes (say, 12), before deasserting SLWR. Would this lead to a deadlock situation, as the FIFO is "full", and it can never empty as there isn't a complete packet yet (only 44 bytes in the FIFO, which is lesser than the 64 bytes required to complete a packet)?
2. Is setting PKTSTAT = 1 the same as {PKTSTAT=0, IN: PKTS[1:0] = 0}?
Thanks. Show Less
USBDevice = new CCyUSBDevice(NULL);
throws an exception. If no device is connected, it does not throw the exception.
I then decided to try a C# solution, and started with the Control Center example. Again, if a device is connected the following statement:
usbDevices = new USBDeviceList(DeviceMask);
will generate 8-10 messages in the output window:
A first chance exception of type 'System.ArgumentNullException' occurred in mscorlib.dll
If no device is connected, no exceptions.
I am not sure where to look next, any suggestions.
Thanks,
Bjarne
Show Less
I've written a C++ program using CyAPI.lib that alternately writes "AA" and "55" using the Xferdata() method into an isochronous endpoint buffer on the CY3684 development board. I'm using slave FIFO Auto mode of operation, with the SLRD pin grounded for permanent assertion. I'm hoping to see a waveform when I hook my scope to any of the FD[0-7] lines on the dev board, I see only noise. I'm fairly sure my firmware is fine, but I'm wondering if there are any obvious registers I omitted or something I'm forgetting to do that could produce this problem.
Thanks for any advice you can offer,
Zach Show Less
In AN4051 (Doc No. 001-15284) about the GPIF Flow State feature for
UDMA, there is a strange (to me) quote on page 4 :
"It should be noted that in the case where MSTB is a CTL pin, the
GPIF will produce at most one extra active edge on MSTB in response to
a not ready indication from the slave."
So am I interpreting this correctly : if the GPIF is in a flow state
and reading data from an external slave, and the slave says "no data
available", then the GPIF *might* (or might not) go ahead and read the
data anyway ?
If this is the case, how does one deal with this situation ? In my
case, I'm reading from a FIFO inside an FPGA, so I can configure it to
have an "almost empty" flag in addition to an "empty flag". It would
seem that the logic would be to pass the FX2 a signal like :
RDY0 = (almost_empty) OR (empty),
and have the flowstate use RDY0 to throttle the data. In principle
this should transfer all but the final word from the FIFO. ("almost
empty" means there is one word remaining.) That, I suppose, could be
read from the FIFO by a normal (i.e., not flow-) state of the GPIF.
Is this the right approach ?
Unfortunately, I gave it a shot and it's not quite working yet.
Before pouring too much effort into it, I'd like to know if there's an
easier way...
BTW, I am basically just using the GPIF Primer example that
writes/reads to an external FIFO. I got rid of the OUT EP and the
write, and instead pipe external video data into the FIFO in the
FPGA. For the flow state logic I use
func = (FifoFlag) OR (empty),
if (func == 0) assert RE#, clock data
if (func == 1) de-assert RE#
where "FifoFlag" is the FX2's FULL flag for the IN EP, and "empty" is
the fpga FIFO empty flag.
Thanks Show Less
btw, My usb chip is cy7c68023, flsh chip be samsung k9f1g08UOA Show Less
I have some CY7C64713 (100 terminales) chips and I was looking at the CY3684 USB 2.0 DEVELOPMENT BOARD schematics. But as this chip does not allow external EEPROM programming I was wondering how I can reduce the circuit to make a simple programmer and start testing it.
The circuitry needed to use the USB port would be enough for now, so I can use it to download the code to the 8051 core.
Thank you for your help. Show Less
Thank you very much.
Show Less