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We are are a small design and manufacturing company. We have a product based on a CY7C64714 chip. It has worked really well in it's existing form for about 4 years. We are planning some added features which involve writing some extra code. We have tried for a long time to get this new code to work, but without success, so we are looking for someone to get it up and running for us.
The code is written in C using the Keil uVision development environment.
More details on request.
Neil. Show Less
Can anyone tell me the throughout of CY7C68013A configured in Bulk,EP2, 4x 512, GPIF?
Recently, I am involved in developing an application to transfer data at 20MB/s . Configured as described above, the data misaligned at the first 2K border. Do anyone know how to solve the problem.
I am facing a huge issue with making the USB work on this device. Unfortunately for some reason the USBUART module is not available for it and I am trying with USBFS.
Even executing the datasheet sample using one of the built-in HID templates causes the software to always hang on USBFS_bGetConfiguration(). I've tried all the possible configurations for USB - HID, no HID, templates, mine. No change whatsoever - the software always hangs on bGetConfiguration().
Speaking about the hardware - nothing specific there, it has been set exactly as from the suggested solution in the datasheet.
Would anyone be able to post here a confirmed working sample for USB on CY7C64343 ?
Thank you all.
PS. To the Cypress' guys:
why there is no USBUART UM for this device?Show Less
While performing GPIF FIFO READ/WRITE operation GPIFREADYSTAT which scans the status of RDYx signals always shows the value of 0x003f (which means all the RDY inputs are high, even after grounding the respective RDY input signal). what could be reason for this? Can any one suggest a suitable solution.Show Less
I am trying to do something with an Encore V MCU (7C64343). The problem I am facing has been described many times yet I have been unable to make it work for me at this stage:
On port 1 I have a few digital inputs and one output controlled by an interrupt function.
My problem is that I can never read the actual status of the inputs, they are always 0.
What I am doing is this:
The relevant bits P1.2, P1.3 and P1.4 are configured as StdCPUInput and drive Analog High Z in the PD
unsigned char P1;
and then in the interrupt function (executed around 100 times per second):
P1=PRT1DR; // supposedly reads the actual input states
P1^=0x20; // swinging the output pin
PRT1DR=P1; // update the output
Everywhere else in the code I only use P1 as read from the code above.
Where is my problem here?
I'm using the EZ-USB for pushing data from my host PC to the device. (Bulk transfers, one way only)
I'm using external logic (Lattice FPGA) that looks only at the Fifo-full interrupt.
I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred to FPGA through the slave FIFO interface in AUTOIN mode (auto-commit with size of 512-byte) from PC.
Endpoint 2 is used, the fifo uses double buffering with packet size of 512 bytes. The external interface is set to 8 bits wide.
No data handling is performed in the FW code. (TD_Poll is empty)
Although I always validate that the overall data length sent from the Host is a multiple of 512 bytes, I guess that under rare conditions an error occurs and a different number of bytes is sent.
This rare condition causes my whole USB channel to come to a stall (I receive Timeouts in my WDU_TransferBulk call) in such a way that only a Hard Reset performed to the chip (pin #99) can resolve.
I am not concerned so much about data being lost in the specific corrupted transfer itself, but more in the ways to recover the channel for further transfers.
A hard reset is not an option, since it requires a redesign of the board, and a hence large delays in delivery.
So I thought to look for some "Soft Reset" that will be equivalent.
I tried two options, in some variants: (but without success) I added code to the ISR_Ures() that performs:
1. Perform FIFORESET to all endpoints. (Copy & Paste from TD_Init)
2. Perform EZUSB_Discon()
Both options brought the chip to some "non responsive" condition. I take it as an option that it is something wrong in my implementation.
I will be more then happy to get your recommendations, since this is a top priority issue in our company, that prevents from tens of machines from being delivered....
---- Please find our original code attached ----
Thank you for any help you can provide. Presently we have the FX2 doing a boot loader from a large I2C EEPROM specifically an 24LC512 device from Microchip. That is located at address 1010001(A2=A1=0 and A0=1) as per the TRM. We also have another EEPROM sitting at address 1010101 for extra data store it is also a 24LC512. I would like to combine these two EEPROMs into an 24LC1025 device from Microchip. But this device only allows the setting of A1 and A0 and A2 is not setable. When you access the EEPROM you have to write a value into a Block bit to set whether you read from the upper half of the EEPROM or the lower half. So the address looks something like this 1010BA1A0 where in the setup above A1=0 and A0=1 => 1010B01. Unfortunately I do not think this will work for boot load applications. According to the TRM the FX2 on bootload checks the A2,A1,A0 bits to determine if there is an appropiate I2C EEPROM to boot from. I don't know how this plays with the 24LC1025 situation.
I didn't state above that we wanna boot load out of the EEPROM because we come up USB and enumarate to our own info.
So does anyone know if the FX2 can be setup to use the 24LC1025 or not and how.
Using 68013A 8bit synchronous slave FIFO interface.
EP2 as Hi-speed Bulk IN. FlagA - programmable FULL.
I use FPGA with ChipScope to test FlagA status.
Test: write enable = inactive, continuous clock at IFCLK. I see FlagA toggling. Seems that period proportional to clock period (tested with 33...6 MHz IFCLK). When reading BULK endpoint from CyConsole STALL reported. Reconnecting not help. Asynchronous FIFO interface work (at least no STALLs).
Any comments?Show Less
I am looking for a board that can act simultaneously as a USB device and as a TCP/IP client over ethernet. I am considering the CY3662. Does anyone know if this board has been used this way before? If so, are there code examples available?
I'm new to Cypress, so I'm not sure how to navigate around and find code/documentation for devices. It looks like resources for the CY3662 are limited. I've looked at the "Getting Started" guide, and its fairly brief.Show Less