Hello, I encountered some problems in the process of reading and writing FPGA and FX3. I want to clarify, the configuration is as follows:
The size of the buffer is set to 16kB
The data bus bit width is 32 bits, and the watermark value is 6,
The state machine is sync slave fifo state machine
FLAGA: Thread_0_DMA_Ready
FLAGB: Thread_0_DMA_Watermark
FLAGC: Thread_3_DMA_Ready
FLAGD: Thread_3_DMA_Watermark
1. The size of my upstream buffer is 4*16KB. FLAGA is configured as a dedicated thread flag Thread_0_DMA_Ready. The FLAGA in the data sheet indicates the current state of the buffer (that is, whether the buffer is full, 0 means full, 1 means dissatisfaction), but when I send a short packet For example, at 32B (the timing is that slwr is pulled down for 32 cycles, and pktend is pulled down for one cycle), I can still see FLAGA from high to low (pulled down by about 11μs). Specifically, the size of a single buffer is 16KB. At this time, only 32B is written, and the buffer is definitely not full. Why FLAGA will change from high to low. When I write 1024B (the timing is to send 256 cycles of data plus a zero packet), the same phenomenon occurs. Will FLAGA be pulled down from high every time I commit?
2. The bit width of my data bus is 32 bits. I would like to ask whether the smallest unit of data sent each time is 4B (32bit). I use short data packets to send 30B from FX3 to FPGA (when data is not a multiple of 4B). Errors will occur, is there a requirement for the size of the data?
3. When the FPGA writes to FX3, when the size of the data is 1024B, I tested two methods, one is in the form of short data packets, the other is by sending a zero-length data packet (ZLP), both methods can be passed I can see the correct data from the control center. Can these two methods work?
4. When the FPGA writes to FX3, when the size of the data is 16KB, two tests are done. First, the PKTEND signal can be raised all the way, and the commit can be made. The second use of the short data packet form (that is, when the last bit of data is 16384B, pull down the PKTEND signal), I can also see the correct result. May I ask whether this situation is normal.
5. With the example code provided by AN65974, when FPGA reads data from FX3, a tap operation is required. May I ask if this is necessary?
