real-time change  data speed of the USB3.0 FIFO interface about slavefifo mode

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user_1516091
Level 2
Level 2
10 replies posted 5 replies posted 10 questions asked

When I change the real-time data rate of the original data from the FPGA into the USB3014 chip.After the USB collects the dozens of packet data,USB will stop collect data. I ever tried to prevent USB go into the low-power mode and  no avail. How can I solve this problem ?

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2 Replies
Anonymous
Not applicable

Hi!

Can you use UART debug prints and check if you are getting any DMA errors.

Btw, what is the PCLK frequency you are using?

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KandlaguntaR_36
Moderator
Moderator
Moderator
25 solutions authored 10 solutions authored 5 solutions authored

There should not be any failure/halt in transferring data from GPIF to USB side, even we change the data on FPGA Side.

The following details are required to debug this issue.

1. What is application that you are implementing on high level, no need to tell actual application?

2. What is the change that you are doing in real-time on FPGA side? Changing the PCLK Frequency, SLWR, SLRD or any other?

3. What is the DMA Buffer size, count and DMA Channel type of DMA Channel from GPIF to USB and USB to GPIF

4. What is the exact number of bytes that USB Collected? Here, are you doing data transfer from Host PC to FPGA, since you told USB collected dozens of packets and stopped?

Any other details, which can help in understanding the issue clearly.

Regards,

Sridhar

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