USB superspeed peripherals Forum Discussions

What solution (part number) is recommended for a USB "host" controller?   Preferably the part should come with relevant firmware and drivers.  

I am implementing a UVC device firmware using the slfifosync as a base on top of an FPGA. I have got the device enumerating how I want and am now trying to get simple MJPEG frames transferring from the FX3 to a Windows laptop through the Camera application, however when I open the Camera and choose the FX3 device as the source, I get a black screen without any video data and I am unsure why. I have gone through the cyfxuvcinmem_bulk source and think I have included all required functions for both USB setup and playback. Using Wireshark to investigate the USB bus, there is a initial device handshake to communicate basic descriptors and then again when the Camera app is initialized to find the streaming parameters. However, after the commit request is handled, there is data being sent between the FX3 and laptop but I don't see any picture in the Camera application. I am new to using the FX3 so any help in resolving this issue would be greatly appreciated! I have included a Wireshark capture which included flashing the firmware, booting the firmware and open and closing the camera application as well as the source code I have.

Hi team,

The cypress provided default OV5640 code is having continuous auto focus means it is focusing when there is a change in frame. But it doesnt have auto focus video control. 

May I know how the continuous auto focus is working? Where we are configuring the OV5640 to follow auto focus?

Thank you,

Shafi. 

Hi team,

In MIPI parameters configuration the PLL Out clock is keep on varying for every resolution. I had observed this in basic CX3_OV5640 UVC code. Can I know why PLL is keep on changing according to the resolution?

If I need to make the PLL clock to be constant for all the resolutions what do I need to do?

Thank you,

Shafi.

I need help with "GettingStartedWithFX3SDK" guide. I'm not able to complete step 4

3.1 Programming the FX3 device
The FX3 examples can be built and run on the FX3 DVK. The following steps
describe the setup and boot process:

1. Install the components of the SDK (Firmware, Toolchain, IDE and Host
drivers) on the host machine
2. Launch the IDE, import the example projects and build them
3. Connect the FX3 board to the host machine and power the board up
4. Bind the driver for the FX3 device.
5. Launch the CyControl utility
6. Download the boot image to the FX3 device RAM using the Control Center
“Download Firmware” option
7. The FX3 device will start running the newly loaded firmware

My system:

HP ENVY x360
12th Gen Intel(R) Core(TM) i5-1235U 1.30 GHz - 8.00 GB RAM
Windows 11 Home (21H2)

The getting started doc has sub-sections for steps 1, 2, and 3 (3.1.1, 3.1.2, 3.1.3) but there are no sub-sections for steps 4, 5, 6 and 7. Section 3.2 talks about "Host driver binding," so I guess this is supposed to be describing step 4 "Bind the driver for the FX3 device."

Anyway, section 3.2 says to look at section 3 of CyUSB.pdf for instructions on how to bind the device:

"The steps for installation and binding of the host drivers for different Windows
platforms are described in section 3 of the host driver help file, CyUSB.pdf,
installed as part of the USB Suite."

The CyUSB.pdf is only divided into "Parts" and Part III is a section that talks about "Driver Resell."

Any clarification will be helpful.

Thanks

Our design uses the CX3 (CYUSB3064-BZXI) to convert MIPI CSI-2 video from a standard definition composite video PAL camera (via the Renesas ISL79987), but we are seeing a double image in the video from the CX3 over USB - see attached screen grab from the video.

It looks like the CX3 firmware is not decoding the interlaced video correctly. There doesn't appear to be any setting for interlaced video in the CX3 SDK.

Please can you help to solve this issue?

Notes:

We are using FFPLAY, or VLC to display the video.

The output from the camera (PAL 720x576 at 25 frames per second) is first converted to MIPI CSI-2 using the Renesas ISL79987 video decoder with MIPI CSI-2 (version 1.1) output. We are configuring the ISL79987 MIPI CSI-2 output to use only 1 lane, but both lanes are connected. Will the unused second lane cause problems in the CX3? We can modify our board to ground the second lane tracks to the CX3 if needed.

The camera output is interlaced video, so I think the MIPI CSI-2 stream from the ISL79987 will also be interlaced.

The video format from the ISL79987 is YUV422 8-bit.

Hi,

I am developing firmware on the CX3 Dev Kit  which is connected to an image sensor. I would like to define a custom camera parameter (besides the standard UVC controls like Brightness, Contract, Saturation, Hue, Exposure, White Balance, ...) which the application can get and set.

How do I define the custom parameter in the CX3 firmware. I understand that I need to to define it in the UVC structures.

Is there any example or application note that I can refer to  related to defining UVC custom parameters?

Any help will be greatly appreciated.

Thanks and Regards,

Subramanyan

Hello,

We are using FX3 to realize the communication between FPGA and our host computer, and we hope to use GPIF II master mode to control the data transmission of FPGA. We assume the following scheme:

we use a MANUAL_IN DMA channel between GPIF and USB bulk in endpoint.

(1) At the beginning, the GPIFII state machine is in a waiting state. Do not write data to the DMA buffer at this time;

(2) When the Host application, such as Control Center, needs 256 bytes of data, click Transfer Data In, then the state machine change to a new state, and starts InData action;

(3) After clicking Transfer Data In, FX3 needs to send a signal to FPGA,   we call it BEGIN signal here;

(4) When the BEGIN signal is high, the FPGA writes data to the 32-bit data line of GPIF II; After 256 bytes of data is written, the BEGIN signal becomes low, the FPGA stops writing data, and the GPIF state machine returns to the wait state.

In short, we hope that FX3 can control the FPGA according to the data size filled in the host application, and let the FPGA write the corresponding size of data to the DMA buffer.

Is the above idea feasible?  if yes, how to set the  GPIF state machine,  to write data into DMA buffer only when the host application needs data?

If not, is there any good suggestion that FX3 can transfer the latest data collected by FPGA to the host  every time the host  needs data?(Our FPGA is used for data acquisition and will be in a continuous working state. At first, we adopted a scheme similar to AN65974, but because the host computer could not take out the data in time, the FPGA has to stop writing the data when DMA buffer is full, and our users did not want this)

Or, can you give us some other plans or suggestions? 

Thank you,

Fan