USB superspeed peripherals Forum Discussions
Hello,
Can the EZ-USB SX3 CYUSB3017 Device stream Video on USB 2.0 Lines and support commands transferring by Virtual COM simultaneously ?
The scenario is: Two Different PC Programs are opened:
- For Video Streaming through USB 2.0.
- For Commands Delivering. Virtual COM exists on USB 2.0. Video Streaming is happening & commands are sent simultaneously.
Can the EZ-USB SX3 CYUSB3017 Device stream Video on USB 3.0 Lines and support commands transferring by Virtual COM simultaneously ?
The scenario is: Two Different PC Programs are opened:
- For Video Streaming through USB 3.0.
- For Commands Delivering. Virtual COM exists on USB 3.0. Video Streaming is happening & commands are sent simultaneously.
Thanks a lot!
Show Lesscase CY_FX_RQT_UART_TX:
status = CyU3PUsbGetEP0Data(wLength, glEp0Buffer, &readCount);
if (status == CY_U3P_SUCCESS)
{
// CyU3PDebugPrint(4, glEp0Buffer);
CyU3PUartTransmitBytes (glEp0Buffer, readCount, &status);
if (status ! = CY_U3P_SUCCESS)
{
}
Regarding the function CyU3PDebugPrint, I can output it, but he can't output 0x00, a long string of data breaks at 0x00.
Besides, when I call CyU3PUartTransmitBytes function above, there is no output, is there something wrong?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/%E8%AF%B7%E6%95%99%E5%85%B3%E4%BA%8E-FX3-UART-%E5%8F%91%E9%80%81%E7%96%91%E6%83%91/td-p/719523
Show LessHello,
I have a few simple questions:
1) I have seen a few example schematics where an inductor is used (in conjunction with capacitors) to condition the voltage supply to AVDD, U3RXVDDQ, and U3TXVDDQ (a picture is attached). Different designers have used different inductor and capacitor values. What values for the inductor (inductance) and capacitor(s) are recommended?
2) Related to 1 above, is the resistance of the inductor of any importance? If so, please provide a min. and max. range; I can only find 10 ohm values in the package I need
Thanks,
Mo
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Hello
When designing the state machine in GPIF designer I can not access to the thread number as shown in the attachment,
How I can solve this issue?
Thanks.
Show LessFX3FirmwareSourceUserGuide.pdf
Win10 platform: this compilation source code has a recommended chain is there a version request
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/FX3-source-%E7%BC%96%E8%AF%91/td-p/724424
Show LessHello, I'm trying to achieve a simple direct GPIF to USB data transfer with a CYUSB3KIT-003. I started with the GpifToUSB example that can be found in C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxgpiftousb and that is mentioned in AN86947 Optimizing USB 3.0 Throughput with EZ-USB® FX3™
The problem is/was that I lose data when the DMA buffer switches. I learned that the solution to this is to implement two or more threads and switch between those. A modified GpifToUSB example implementing exactly that can be found in https://community.infineon.com/t5/USB-superspeed-peripherals/EZ-USB-FX3-Explorer-kit-as-16-channel-logic-analyzers-gt-dropped-samples-after/m-p/635888#M35636
I used the source code there and slightly changed it to use an external clock.
Unfortunately it does not solve my problem, I still lose data every ~16 KB (which is the configured DMA buffer size).
I've attached my source code. It's mostly the example from the forum post above, changed to an external clock.
Also, I'm not quite sure what the reasoning behind the size of the counter in the state machine is. Why is it 1/4th of the DMA buffer size and not 1/2?
Any help would be greatly appreciated!
Here's the UART debug log, from the point where I flash the .img into RAM. Afterwards I shortly start and stop a data transfer using the CollectData.exe from CYUSB3KIT\SuperSpeed Design Examples V1.2.1\PC Utilities\
debug initialized
Prod:0 , Cons:0
USB event: 11 0
About to connect to USB host
USB event: 0 1
CY_U3P_USB_EVENT_CONNECT detected
CyFxApplnInit complete
USB event: 8 0
USB event: 5 1
Using GPIF:cyfxgpif2config
Prod:6 , Cons:0
Prod:2 , Cons:0
Vendor Command Received: 0xA0
Vendor Command Received: 0xA0
Vendor Command Received: 0xA0
Vendor Command Received: 0xB5
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Prod:1 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Prod:1 , Cons:0
...
[shortened]
...
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Prod:1 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Vendor Command Received: 0xB5
Prod:1 , Cons:0
Prod:2 , Cons:0
Prod:2 , Cons:0
Prod:1 , Cons:0
Prod:1 , Cons:0
Prod:2 , Cons:0
Here is my state machine:
Edit: I've attached a binary file of about 130 KB of transferred data. It can be easily viewed in a hex editor for example. The transferred data is a 7 bit monotonically rising number. On addresses 0x4000, 0x8000, 0xC000, ... (multiples of 16384 bytes, the configured DMA buffer size) you can see data loss. For convenience I also added a screenshot showing the loss:
And here is a trace of the incoming data (non-shown lines are kept at logic low). I've marked a random sampling edge to show that data is sampled on the rising edge:
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Hi guys,
So I've done to set the serial number in fx3 as this KBA
But I have a question, so we are integrating the FX3 in our custom board which each serial number its about 12 characters,
and I tried to just write the Serial number as this:
const uint8_t CyFxUSBSerialNumberDscr[] __attribute__ ((aligned (32))) =
{
0x10, /* Descriptor size */
CY_U3P_USB_STRING_DESCR, /* Device descriptor type */
'M',0x00,
'Y',0x00,
'C',0x00,
'A',0x00,
'R',0x00,
'D',0x00,
'1',0x00,
'6',0x00,
'0',0x00,
'5',0x00,
'9',0x00,
'3',0x00,
};
But this will only show as:
How can I make it to look as the full serial number?
Thanks!
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Hello,
I have created the slave FIFO sync 32 bit mode interface between the FX3 and Xilinx FPGA. I have referred to the AN65974 and used the example code provided to generate FX3 image without any modifications. On the FPGA side, I have followed the FSM shown in the document. Stream_IN is working fine with no issues. In Stream_Out mode, I am observing that if I am sending 28bytes which is 7*32-bit packets through the Control center application, The FPGA is recieving jumbled data.
I have two queries regarding this:
1. In many RTL example codes I have seen PCLK being routed using ODDR. Does this mean PCLK has to be inverted while driving from FPGA?
2.The input 32bit data has to be sampled by FPGA on rising or falling edge of PCLK?
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Hello,
Whether EZ USB SX3 CYUSB3017-BZXI supports Video Streaming on USB 2.0 PHY if USB 3.0 (SSTX; SSRX) is disconnected?
I am talking about 640x512 with Low FPS.
Thanks
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