USB superspeed peripherals Forum Discussions

How to get Bus Data ? For example Bits 20-27.
Setting all Bits manual or is there any other way ?

Single Bit In / Out works fine, but i dont find any example to read bytes / words ?

Thanks !

 

Hi, can anybody tell me what is the maximum continuous transfer bandwidth measured so far (using the cypress provided reference designs) using continuous bulk device to host transfers on a standard equipped USB 3 enabled windows 7 host (in terms of MBytes/s) ? Which design has been used? 

Is there any way to enable OS/usb stack diagnostic output on the FX3 serial port ? As I saw there are quite a lot of things which are done transparent to the user. It would be helpful for debuging and troubleshooting reasons to output as much diagnostic as possible on the serial port.

Thanks in advance, Joel

Hi,

I'm using the cyfxbulklpauto and cyfxbulkstreams, I added to the two firmwares some line with to see if the connection used are the  high speed or the super speed and I found that both goes on High speed.

Line added:

else if (glUsbSpeed == CY_U3P_HIGH_SPEED)

{

    endPointConfig.pcktSize = 512;

    CyU3PDebugPrint (4, "High Speed\n");

 }

else if (glUsbSpeed == CY_U3P_SUPER_SPEED)

{

 endPointConfig.pcktSize = 1024;

  CyU3PDebugPrint (4, "Super Speed\n");

}

Because of this the average transfert rate do not exceed the 35MB/s.

To test this firware I'm using the two C++ application distributed with the SDK.

I have to change some parameter to enable super speed?

Athos

Hi,

I have noticed on FX3 DVK evalboard schematics that the MICRO_SSRX- signal from USB 3 connector is linked to SS_RX_P pin and MICRO_SSRX+ from USB3 connector is linked to SS_RX_M pin on FX3.

We guess SS_RX_M is for SS_RX_Minus and SS_RX_P is for SS_RX_POSITIVE so it seems to be inverted ?

Otherwise SS_TX_M is effectively linked to MICRO_SSTX+ connector and SS_TX_P is linked to MICRO_SSTX- connector.

Could you confirm the correct pinout

Regards,

Dam

Hi !

 My FX3 only enumerate on USB Bus with external 32Khz Clock. Without Clock.. Nothing happens !?

PS: I build my own Testboard and all Pins are connected.

Hi,

I've got a question concerning the "Synchronous Slave FIFO interface with 32-bit data bus". It’s the interface between the FX3 and a FPGA in our application.  I’m wondering what happens if the USB packet length is not a multiple of 4 that means it fits not completely to the 32 bit bus width.
During the read sequence (from FX3 to FPGA) the last 32-bit-word that is read from the FX3-FIFO will contain less than 4 bytes. Therefore the FPGA doesn't know which bytes of the last word are valid. On the other hand during the write sequence (from FPGA to FX3) the last 32-bit-word that is written to the FX3-FIFO will contain less than 4 bytes. In that case the FX3 doesn't know which bytes are valid. I think there must be a kind of “byte qualifier” signal to mark the valid bytes within the 32-bit-words. Is it possible to configure some flags in the GPIF II as “byte enable”? I didn't find any hint in the application notes.

Best regards...